#ifndef AD7793_H_
#define AD7793_H_

#include "ioavr.h"
#include "../SPI/spi.h"
#include "../SPI/uartspi.h"

//-------- communications register bits ----
#define CREAD     2
#define RS0       3
#define RS1       4
#define RS2       5
#define RW        6
#define nWEN      7

//-------- mode register bits --------------
#define FS0       0
#define FS1       1
#define FS2       2
#define FS3       3
#define CLK0      6
#define CLK1      7
#define MD0       13
#define MD1       14
#define MD2       15

#define MODE_MD_CONTINUOUS          (0<<MD2) | (0<<MD1) | (0<<MD0)
#define MODE_MD_SINGLE              (0<<MD2) | (0<<MD1) | (1<<MD0)
#define MODE_MD_IDLE                (0<<MD2) | (1<<MD1) | (0<<MD0)
#define MODE_MD_POWERDOWN           (0<<MD2) | (1<<MD1) | (1<<MD0)
#define MODE_MD_INTERNAL_ZSC        (1<<MD2) | (0<<MD1) | (0<<MD0)
#define MODE_MD_INTERNAL_FSC        (1<<MD2) | (0<<MD1) | (1<<MD0)
#define MODE_MD_SYSTEM_ZSC          (1<<MD2) | (1<<MD1) | (0<<MD0)
#define MODE_MD_SYSTEM_FSC          (1<<MD2) | (1<<MD1) | (1<<MD0)

#define MODE_CLK_INTERNAL64_NOOUT   (0<<CLK1) | (0<<CLK0)
#define MODE_CLK_INTERNAL64_OUT     (0<<CLK1) | (1<<CLK0)
#define MODE_CLK_EXTERNAL64         (1<<CLK1) | (0<<CLK0)
#define MODE_CLK_EXTERNAL64_DIV2    (1<<CLK1) | (1<<CLK0)

#define MODE_RATE_0Hz               (0<<FS3) | (0<<FS2) | (0<<FS1) | (0<<FS0)
#define MODE_RATE_500Hz             (0<<FS3) | (0<<FS2) | (0<<FS1) | (1<<FS0)
#define MODE_RATE_250Hz             (0<<FS3) | (0<<FS2) | (1<<FS1) | (0<<FS0)
#define MODE_RATE_125Hz             (0<<FS3) | (0<<FS2) | (1<<FS1) | (1<<FS0)
#define MODE_RATE_62Hz              (0<<FS3) | (1<<FS2) | (0<<FS1) | (0<<FS0)
#define MODE_RATE_50Hz              (0<<FS3) | (1<<FS2) | (0<<FS1) | (1<<FS0)
#define MODE_RATE_39Hz              (0<<FS3) | (1<<FS2) | (1<<FS1) | (0<<FS0)
#define MODE_RATE_33Hz              (0<<FS3) | (1<<FS2) | (1<<FS1) | (1<<FS0)
#define MODE_RATE_19Hz              (1<<FS3) | (0<<FS2) | (0<<FS1) | (0<<FS0)
#define MODE_RATE_16Hz              (1<<FS3) | (0<<FS2) | (0<<FS1) | (1<<FS0)
#define MODE_RATE_16Hz_2            (1<<FS3) | (0<<FS2) | (1<<FS1) | (0<<FS0)
#define MODE_RATE_12Hz              (1<<FS3) | (0<<FS2) | (1<<FS1) | (1<<FS0)
#define MODE_RATE_10Hz              (1<<FS3) | (1<<FS2) | (0<<FS1) | (0<<FS0)
#define MODE_RATE_8Hz               (1<<FS3) | (1<<FS2) | (0<<FS1) | (1<<FS0)
#define MODE_RATE_6Hz               (1<<FS3) | (1<<FS2) | (1<<FS1) | (0<<FS0)
#define MODE_RATE_4Hz               (1<<FS3) | (1<<FS2) | (1<<FS1) | (1<<FS0)

//-------- configuration register bits -----

#define CH0       0
#define CH1       1
#define CH2       2
#define BUF       4
#define REFSEL    7
#define G0        8
#define G1        9
#define G2        10
#define BOOST     11
#define UB        12
#define BO        13
#define VBIAS0    14
#define VBIAS1    15

#define CONF_BIAS_DISABLE     (0<<VBIAS1) | (0<<VBIAS0)
#define CONF_BIAS_AIN1        (0<<VBIAS1) | (1<<VBIAS0)
#define CONF_BIAS_AIN2        (1<<VBIAS1) | (0<<VBIAS0)
#define CONF_BIAS_RESERVED    (1<<VBIAS1) | (1<<VBIAS0)

#define CONF_BURNOUT_ENABLE   (1<<BO)
#define CONF_SET_UNIPOLAR     (1<<UB)
#define CONF_BIAS_INCREASE    (1<<BOOST)

#define CONF_GAIN_1            (0<<G2) | (0<<G1) | (0<<G0)
#define CONF_GAIN_2            (0<<G2) | (0<<G1) | (1<<G0)
#define CONF_GAIN_4            (0<<G2) | (1<<G1) | (0<<G0)
#define CONF_GAIN_8            (0<<G2) | (1<<G1) | (1<<G0)
#define CONF_GAIN_16           (1<<G2) | (0<<G1) | (0<<G0)
#define CONF_GAIN_32           (1<<G2) | (0<<G1) | (1<<G0)
#define CONF_GAIN_64           (1<<G2) | (1<<G1) | (0<<G0)
#define CONF_GAIN_128          (1<<G2) | (1<<G1) | (1<<G0)

#define CONF_REF_EXTERNAL     (0<<REFSEL)
#define CONF_REF_INTERNAL     (1<<REFSEL)

#define CONF_BUFFER_ENABLE    (1<<BUF)

#define CONF_CHANNEL_AIN1         (0<<CH2) | (0<<CH1) | (0<<CH0)
#define CONF_CHANNEL_AIN2         (0<<CH2) | (0<<CH1) | (1<<CH0)
#define CONF_CHANNEL_AIN3         (0<<CH2) | (1<<CH1) | (0<<CH0)
#define CONF_CHANNEL_AIN1_M       (0<<CH2) | (1<<CH1) | (1<<CH0)
#define CONF_CHANNEL_TEMP         (1<<CH2) | (1<<CH1) | (0<<CH0)
#define CONF_CHANNEL_AVDD         (1<<CH2) | (1<<CH1) | (1<<CH0)

//-------- IO register bits -----

#define IEXCEN0   0
#define IEXCEN1   1
#define IEXCDIR0  2
#define IEXCDIR1  3

#define IO_DIR_11_22          (0<<IEXCDIR1) | (0<<IEXCDIR0)
#define IO_DIR_12_21          (0<<IEXCDIR1) | (1<<IEXCDIR0)
#define IO_DIR_1              (1<<IEXCDIR1) | (0<<IEXCDIR0)
#define IO_DIR_2              (1<<IEXCDIR1) | (1<<IEXCDIR0)

#define IO_SOURCE_DISABLE     (0<<IEXCEN1) | (0<<IEXCEN0)
#define IO_SOURCE_10uA        (0<<IEXCEN1) | (1<<IEXCEN0)
#define IO_SOURCE_210uA       (1<<IEXCEN1) | (0<<IEXCEN0)
#define IO_SOURCE_1mA         (1<<IEXCEN1) | (1<<IEXCEN0)

//-----------------

#define SPI_COMMUNICATIONS

#ifndef SPI_COMMUNICATIONS
      #define UART_COMMUNICATIONS
#endif

void ad7793_init();
unsigned char ad7793_get_ID();
unsigned char ad7793_get_status();
unsigned int  ad7793_get_mode();
unsigned int  ad7793_get_config();
unsigned long int  ad7793_get_data();
unsigned char ad7793_get_IO();
unsigned long int ad7793_get_offset();
unsigned long int ad7793_get_calibration();

void ad7793_set_mode(unsigned int mode);
void ad7793_set_config(unsigned int config);
void ad7793_set_IO(unsigned char io_mode);

#endif