#define PPCR_Fx24	        	/*  Freq. x 24 (fcpu = 24*fxtl)    */ \                	(0x02 << FShft (PPCR_CCF))#define PPCR_Fx28	        	/*  Freq. x 28 (fcpu = 28*fxtl)    */ \                	(0x03 << FShft (PPCR_CCF))#define PPCR_Fx32	        	/*  Freq. x 32 (fcpu = 32*fxtl)    */ \                	(0x04 << FShft (PPCR_CCF))#define PPCR_Fx36	        	/*  Freq. x 36 (fcpu = 36*fxtl)    */ \                	(0x05 << FShft (PPCR_CCF))#define PPCR_Fx40	        	/*  Freq. x 40 (fcpu = 40*fxtl)    */ \                	(0x06 << FShft (PPCR_CCF))#define PPCR_Fx44	        	/*  Freq. x 44 (fcpu = 44*fxtl)    */ \                	(0x07 << FShft (PPCR_CCF))#define PPCR_Fx48	        	/*  Freq. x 48 (fcpu = 48*fxtl)    */ \                	(0x08 << FShft (PPCR_CCF))#define PPCR_Fx52	        	/*  Freq. x 52 (fcpu = 52*fxtl)    */ \                	(0x09 << FShft (PPCR_CCF))#define PPCR_Fx56	        	/*  Freq. x 56 (fcpu = 56*fxtl)    */ \                	(0x0A << FShft (PPCR_CCF))#define PPCR_Fx60	        	/*  Freq. x 60 (fcpu = 60*fxtl)    */ \                	(0x0B << FShft (PPCR_CCF))#define PPCR_Fx64	        	/*  Freq. x 64 (fcpu = 64*fxtl)    */ \                	(0x0C << FShft (PPCR_CCF))#define PPCR_Fx68	        	/*  Freq. x 68 (fcpu = 68*fxtl)    */ \                	(0x0D << FShft (PPCR_CCF))#define PPCR_Fx72	        	/*  Freq. x 72 (fcpu = 72*fxtl)    */ \                	(0x0E << FShft (PPCR_CCF))#define PPCR_Fx76	        	/*  Freq. x 76 (fcpu = 76*fxtl)    */ \                	(0x0F << FShft (PPCR_CCF))                	        	/*  3.6864 MHz crystal (fxtl):     */#define PPCR_F59_0MHz	PPCR_Fx16	/*   Freq. (fcpu) =  59.0 MHz      */#define PPCR_F73_7MHz	PPCR_Fx20	/*   Freq. (fcpu) =  73.7 MHz      */#define PPCR_F88_5MHz	PPCR_Fx24	/*   Freq. (fcpu) =  88.5 MHz      */#define PPCR_F103_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 103.2 MHz      */#define PPCR_F118_0MHz	PPCR_Fx32	/*   Freq. (fcpu) = 118.0 MHz      */#define PPCR_F132_7MHz	PPCR_Fx36	/*   Freq. (fcpu) = 132.7 MHz      */#define PPCR_F147_5MHz	PPCR_Fx40	/*   Freq. (fcpu) = 147.5 MHz      */#define PPCR_F162_2MHz	PPCR_Fx44	/*   Freq. (fcpu) = 162.2 MHz      */#define PPCR_F176_9MHz	PPCR_Fx48	/*   Freq. (fcpu) = 176.9 MHz      */#define PPCR_F191_7MHz	PPCR_Fx52	/*   Freq. (fcpu) = 191.7 MHz      */#define PPCR_F206_4MHz	PPCR_Fx56	/*   Freq. (fcpu) = 206.4 MHz      */#define PPCR_F221_2MHz	PPCR_Fx60	/*   Freq. (fcpu) = 221.2 MHz      */#define PPCR_F239_6MHz	PPCR_Fx64	/*   Freq. (fcpu) = 239.6 MHz      */#define PPCR_F250_7MHz	PPCR_Fx68	/*   Freq. (fcpu) = 250.7 MHz      */#define PPCR_F265_4MHz	PPCR_Fx72	/*   Freq. (fcpu) = 265.4 MHz      */#define PPCR_F280_2MHz	PPCR_Fx76	/*   Freq. (fcpu) = 280.2 MHz      */                	        	/*  3.5795 MHz crystal (fxtl):     */#define PPCR_F57_3MHz	PPCR_Fx16	/*   Freq. (fcpu) =  57.3 MHz      */#define PPCR_F71_6MHz	PPCR_Fx20	/*   Freq. (fcpu) =  71.6 MHz      */#define PPCR_F85_9MHz	PPCR_Fx24	/*   Freq. (fcpu) =  85.9 MHz      */#define PPCR_F100_2MHz	PPCR_Fx28	/*   Freq. (fcpu) = 100.2 MHz      */#define PPCR_F114_5MHz	PPCR_Fx32	/*   Freq. (fcpu) = 114.5 MHz      */#define PPCR_F128_9MHz	PPCR_Fx36	/*   Freq. (fcpu) = 128.9 MHz      */#define PPCR_F143_2MHz	PPCR_Fx40	/*   Freq. (fcpu) = 143.2 MHz      */#define PPCR_F157_5MHz	PPCR_Fx44	/*   Freq. (fcpu) = 157.5 MHz      */#define PPCR_F171_8MHz	PPCR_Fx48	/*   Freq. (fcpu) = 171.8 MHz      */#define PPCR_F186_1MHz	PPCR_Fx52	/*   Freq. (fcpu) = 186.1 MHz      */#define PPCR_F200_5MHz	PPCR_Fx56	/*   Freq. (fcpu) = 200.5 MHz      */#define PPCR_F214_8MHz	PPCR_Fx60	/*   Freq. (fcpu) = 214.8 MHz      */#define PPCR_F229_1MHz	PPCR_Fx64	/*   Freq. (fcpu) = 229.1 MHz      */#define PPCR_F243_4MHz	PPCR_Fx68	/*   Freq. (fcpu) = 243.4 MHz      */#define PPCR_F257_7MHz	PPCR_Fx72	/*   Freq. (fcpu) = 257.7 MHz      */#define PPCR_F272_0MHz	PPCR_Fx76	/*   Freq. (fcpu) = 272.0 MHz      */#define POSR_OOK	0x00000001	/* RTC Oscillator (32.768 kHz) OK  *//* * Reset Controller (RC) control registers * * Registers *    RSRR      	Reset Controller (RC) Software Reset Register *              	(read/write). *    RCSR      	Reset Controller (RC) Status Register (read/write). */#define RSRR		__REG(0x90030000)  /* RC Software Reset Reg. */#define RCSR		__REG(0x90030004)  /* RC Status Reg. */#define RSRR_SWR	0x00000001	/* SoftWare Reset (set only)       */#define RCSR_HWR	0x00000001	/* HardWare Reset                  */#define RCSR_SWR	0x00000002	/* SoftWare Reset                  */#define RCSR_WDR	0x00000004	/* Watch-Dog Reset                 */#define RCSR_SMR	0x00000008	/* Sleep-Mode Reset                *//* * Test unit control registers * * Registers *    TUCR      	Test Unit Control Register (read/write). */#define TUCR		__REG(0x90030008)  /* Test Unit Control Reg. */#define TUCR_TIC	0x00000040	/* TIC mode                        */#define TUCR_TTST	0x00000080	/* Trim TeST mode                  */#define TUCR_RCRC	0x00000100	/* Richard's Cyclic Redundancy     */                	        	/* Check                           */#define TUCR_PMD	0x00000200	/* Power Management Disable        */#define TUCR_MR 	0x00000400	/* Memory Request mode             */#define TUCR_NoMB	(TUCR_MR*0)	/*  No Memory Bus request & grant  */#define TUCR_MBGPIO	(TUCR_MR*1)	/*  Memory Bus request (MBREQ) &   */                	        	/*  grant (MBGNT) on GPIO [22:21]  */#define TUCR_CTB	Fld (3, 20)	/* Clock Test Bits                 */#define TUCR_FDC	0x00800000	/* RTC Force Delete Count          */#define TUCR_FMC	0x01000000	/* Force Michelle's Control mode   */#define TUCR_TMC	0x02000000	/* RTC Trimmer Multiplexer Control */#define TUCR_DPS	0x04000000	/* Disallow Pad Sleep              */#define TUCR_TSEL	Fld (3, 29)	/* clock Test SELect on GPIO [27]  */#define TUCR_32_768kHz	        	/*  32.768 kHz osc. on GPIO [27]   */ \                	(0 << FShft (TUCR_TSEL))#define TUCR_3_6864MHz	        	/*  3.6864 MHz osc. on GPIO [27]   */ \                	(1 << FShft (TUCR_TSEL))#define TUCR_VDD	        	/*  VDD ring osc./16 on GPIO [27]  */ \                	(2 << FShft (TUCR_TSEL))#define TUCR_96MHzPLL	        	/*  96 MHz PLL/4 on GPIO [27]      */ \                	(3 << FShft (TUCR_TSEL))#define TUCR_Clock	        	/*  internal (fcpu/2) & 32.768 kHz */ \                	        	/*  Clocks on GPIO [26:27]         */ \                	(4 << FShft (TUCR_TSEL))#define TUCR_3_6864MHzA	        	/*  3.6864 MHz osc. on GPIO [27]   */ \                	        	/*  (Alternative)                  */ \                	(5 << FShft (TUCR_TSEL))#define TUCR_MainPLL	        	/*  Main PLL/16 on GPIO [27]       */ \                	(6 << FShft (TUCR_TSEL))#define TUCR_VDDL	        	/*  VDDL ring osc./4 on GPIO [27]  */ \                	(7 << FShft (TUCR_TSEL))/* * General-Purpose Input/Output (GPIO) control registers * * Registers *    GPLR      	General-Purpose Input/Output (GPIO) Pin Level *              	Register (read). *    GPDR      	General-Purpose Input/Output (GPIO) Pin Direction *              	Register (read/write). *    GPSR      	General-Purpose Input/Output (GPIO) Pin output Set *              	Register (write). *    GPCR      	General-Purpose Input/Output (GPIO) Pin output Clear *              	Register (write). *    GRER      	General-Purpose Input/Output (GPIO) Rising-Edge *              	detect Register (read/write). *    GFER      	General-Purpose Input/Output (GPIO) Falling-Edge *              	detect Register (read/write). *    GEDR      	General-Purpose Input/Output (GPIO) Edge Detect *              	status Register (read/write). *    GAFR      	General-Purpose Input/Output (GPIO) Alternate *              	Function Register (read/write). * * Clock *    fcpu, Tcpu	Frequency, period of the CPU core clock (CCLK). */#define GPLR		__REG(0x90040000)  /* GPIO Pin Level Reg.             */#define GPDR		__REG(0x90040004)  /* GPIO Pin Direction Reg.         */#define GPSR		__REG(0x90040008)  /* GPIO Pin output Set Reg.        */#define GPCR		__REG(0x9004000C)  /* GPIO Pin output Clear Reg.      */#define GRER		__REG(0x90040010)  /* GPIO Rising-Edge detect Reg.    */#define GFER		__REG(0x90040014)  /* GPIO Falling-Edge detect Reg.   */#define GEDR		__REG(0x90040018)  /* GPIO Edge Detect status Reg.    */#define GAFR		__REG(0x9004001C)  /* GPIO Alternate Function Reg.    */#define GPIO_MIN	(0)#define GPIO_MAX	(27)#define GPIO_GPIO(Nb)	        	/* GPIO [0..27]                    */ \                	(0x00000001 << (Nb))#define GPIO_GPIO0	GPIO_GPIO (0)	/* GPIO  [0]                       */#define GPIO_GPIO1	GPIO_GPIO (1)	/* GPIO  [1]                       */#define GPIO_GPIO2	GPIO_GPIO (2)	/* GPIO  [2]                       */#define GPIO_GPIO3	GPIO_GPIO (3)	/* GPIO  [3]                       */#define GPIO_GPIO4	GPIO_GPIO (4)	/* GPIO  [4]                       */#define GPIO_GPIO5	GPIO_GPIO (5)	/* GPIO  [5]                       */#define GPIO_GPIO6	GPIO_GPIO (6)	/* GPIO  [6]                       */#define GPIO_GPIO7	GPIO_GPIO (7)	/* GPIO  [7]                       */#define GPIO_GPIO8	GPIO_GPIO (8)	/* GPIO  [8]                       */#define GPIO_GPIO9	GPIO_GPIO (9)	/* GPIO  [9]                       */#define GPIO_GPIO10	GPIO_GPIO (10)	/* GPIO [10]                       */#define GPIO_GPIO11	GPIO_GPIO (11)	/* GPIO [11]                       */#define GPIO_GPIO12	GPIO_GPIO (12)	/* GPIO [12]                       */#define GPIO_GPIO13	GPIO_GPIO (13)	/* GPIO [13]                       */#define GPIO_GPIO14	GPIO_GPIO (14)	/* GPIO [14]                       */#define GPIO_GPIO15	GPIO_GPIO (15)	/* GPIO [15]                       */#define GPIO_GPIO16	GPIO_GPIO (16)	/* GPIO [16]                       */#define GPIO_GPIO17	GPIO_GPIO (17)	/* GPIO [17]                       */#define GPIO_GPIO18	GPIO_GPIO (18)	/* GPIO [18]                       */#define GPIO_GPIO19	GPIO_GPIO (19)	/* GPIO [19]                       */#define GPIO_GPIO20	GPIO_GPIO (20)	/* GPIO [20]                       */#define GPIO_GPIO21	GPIO_GPIO (21)	/* GPIO [21]                       */#define GPIO_GPIO22	GPIO_GPIO (22)	/* GPIO [22]                       */#define GPIO_GPIO23	GPIO_GPIO (23)	/* GPIO [23]                       */#define GPIO_GPIO24	GPIO_GPIO (24)	/* GPIO [24]                       */#define GPIO_GPIO25	GPIO_GPIO (25)	/* GPIO [25]                       */#define GPIO_GPIO26	GPIO_GPIO (26)	/* GPIO [26]                       */#define GPIO_GPIO27	GPIO_GPIO (27)	/* GPIO [27]                       */#define GPIO_LDD(Nb)	        	/* LCD Data [8..15] (O)            */ \                	GPIO_GPIO ((Nb) - 6)#define GPIO_LDD8	GPIO_LDD (8)	/* LCD Data  [8] (O)               */#define GPIO_LDD9	GPIO_LDD (9)	/* LCD Data  [9] (O)               */#define GPIO_LDD10	GPIO_LDD (10)	/* LCD Data [10] (O)               */#define GPIO_LDD11	GPIO_LDD (11)	/* LCD Data [11] (O)               */#define GPIO_LDD12	GPIO_LDD (12)	/* LCD Data [12] (O)               */#define GPIO_LDD13	GPIO_LDD (13)	/* LCD Data [13] (O)               */#define GPIO_LDD14	GPIO_LDD (14)	/* LCD Data [14] (O)               */#define GPIO_LDD15	GPIO_LDD (15)	/* LCD Data [15] (O)               */                	        	/* ser. port 4:                    */#define GPIO_SSP_TXD	GPIO_GPIO (10)	/*  SSP Transmit Data (O)          */#define GPIO_SSP_RXD	GPIO_GPIO (11)	/*  SSP Receive Data (I)           */#define GPIO_SSP_SCLK	GPIO_GPIO (12)	/*  SSP Sample CLocK (O)           */#define GPIO_SSP_SFRM	GPIO_GPIO (13)	/*  SSP Sample FRaMe (O)           */                	        	/* ser. port 1:                    */#define GPIO_UART_TXD	GPIO_GPIO (14)	/*  UART Transmit Data (O)         */#define GPIO_UART_RXD	GPIO_GPIO (15)	/*  UART Receive Data (I)          */#define GPIO_SDLC_SCLK	GPIO_GPIO (16)	/*  SDLC Sample CLocK (I/O)        */#define GPIO_SDLC_AAF	GPIO_GPIO (17)	/*  SDLC Abort After Frame (O)     */#define GPIO_UART_SCLK1	GPIO_GPIO (18)	/*  UART Sample CLocK 1 (I)        */                	        	/* ser. port 4:                    */#define GPIO_SSP_CLK	GPIO_GPIO (19)	/*  SSP external CLocK (I)         */                	        	/* ser. port 3:                    */#define GPIO_UART_SCLK3	GPIO_GPIO (20)	/*  UART Sample CLocK 3 (I)        */                	        	/* ser. port 4:                    */#define GPIO_MCP_CLK	GPIO_GPIO (21)	/*  MCP CLocK (I)                  */                	        	/* test controller:                */#define GPIO_TIC_ACK	GPIO_GPIO (21)	/*  TIC ACKnowledge (O)            */#define GPIO_MBGNT	GPIO_GPIO (21)	/*  Memory Bus GraNT (O)           */#define GPIO_TREQA	GPIO_GPIO (22)	/*  TIC REQuest A (I)              */#define GPIO_MBREQ	GPIO_GPIO (22)	/*  Memory Bus REQuest (I)         */#define GPIO_TREQB	GPIO_GPIO (23)	/*  TIC REQuest B (I)              */#define GPIO_1Hz	GPIO_GPIO (25)	/* 1 Hz clock (O)                  */#define GPIO_RCLK	GPIO_GPIO (26)	/* internal (R) CLocK (O, fcpu/2)  */#define GPIO_32_768kHz	GPIO_GPIO (27)	/* 32.768 kHz clock (O, RTC)       */#define GPDR_In 	0       	/* Input                           */#define GPDR_Out	1       	/* Output                          *//* * Interrupt Controller (IC) control reg