#define fLCDADDR_OFFSET	Fld(11,11)	/* Virtual screen offset size					   (# of half words) */#define LCDADDR_OFFSET(x)	FInsrt((x), fLCDADDR_OFFSET)#define fLCDADDR_PAGE	Fld(11,0)	/* Virtual screen page width					   (# of half words) */#define LCDADDR_PAGE(x)	FInsrt((x), fLCDADDR_PAGE)#define TPAL_LEN	(1 << 24)	/* 1 : Temp. Pallete Register enable */#define fTPAL_VAL	Fld(24,0)	/* Temp. Pallete Register value *///#define TPAL_VAL	FMsk(fTPAL_VAL)#define TPAL_VAL(x)	FInsrt((x), fTPAL_VAL)#define TPAL_VAL_RED(x)	FInsrt((x), Fld(8,16))#define TPAL_VAL_GREEN(x)	FInsrt((x), Fld(8,8))#define TPAL_VAL_BLUE(x)	FInsrt((x), Fld(8,0))/* * NAND Flash Controller (Page 6-1 ~ 6-8) * * Register   NFCONF   NAND Flash Configuration    [word, R/W, 0x00000000]   NFCMD    NAND Flash Command Set      [word, R/W, 0x00000000]   NFADDR   NAND Flash Address Set      [word, R/W, 0x00000000]   NFDATA   NAND Flash Data             [word, R/W, 0x00000000]   NFSTAT   NAND Flash Status           [word, R, 0x00000000]   NFECC    NAND Flash ECC              [3 bytes, R, 0x00000000] * */#define bNAND_CTL(Nb)	__REG(0x4e000000 + (Nb))#define NFCONF		bNAND_CTL(0x00)#define NFCMD       bNAND_CTL(0x04)#define NFADDR      bNAND_CTL(0x08)#define NFDATA      bNAND_CTL(0x0c)#define NFSTAT      bNAND_CTL(0x10)#define NFECC       bNAND_CTL(0x14)#define fNFCONF_TWRPH1   Fld(3,0)#define NFCONF_TWRPH1    FMsk(fNFCONF_TWRPH1)#define NFCONF_TWRPH1_0  FInsrt(0x0, fNFCONF_TWRPH1) /* 0 */#define fNFCONF_TWRPH0   Fld(3,4)#define NFCONF_TWRPH0    FMsk(fNFCONF_TWRPH0)#define NFCONF_TWRPH0_3  FInsrt(0x3, fNFCONF_TWRPH0) /* 3 */#define fNFCONF_TACLS    Fld(3,8)#define NFCONF_TACLS     FMsk(fNFCONF_TACLS)#define NFCONF_TACLS_0   FInsrt(0x0, fNFCONF_TACLS) /* 0 */#define fNFCONF_nFCE     Fld(1,11)#define NFCONF_nFCE      FMsk(fNFCONF_nFCE)#define NFCONF_nFCE_LOW  FInsrt(0x0, fNFCONF_nFCE) /* active */#define NFCONF_nFCE_HIGH FInsrt(0x1, fNFCONF_nFCE) /* inactive */#define fNFCONF_ECC      Fld(1,12)#define NFCONF_ECC       FMsk(fNFCONF_ECC)#define NFCONF_ECC_NINIT FInsrt(0x0, fNFCONF_ECC) /* not initialize */#define NFCONF_ECC_INIT  FInsrt(0x1, fNFCONF_ECC)    /* initialize */#define fNFCONF_ADDRSTEP Fld(1,13)                 /* Addressing Step */#define NFCONF_ADDRSTEP  FMsk(fNFCONF_ADDRSTEP)#define fNFCONF_PAGESIZE Fld(1,14)#define NFCONF_PAGESIZE  FMsk(fNFCONF_PAGESIZE)#define NFCONF_PAGESIZE_256  FInsrt(0x0, fNFCONF_PAGESIZE) /* 256 bytes */#define NFCONF_PAGESIZE_512  FInsrt(0x1, fNFCONF_PAGESIZE) /* 512 bytes */#define fNFCONF_FCTRL    Fld(1,15)  /* Flash controller enable/disable */#define NFCONF_FCTRL     FMsk(fNFCONF_FCTRL)#define NFCONF_FCTRL_DIS FInsrt(0x0, fNFCONF_FCTRL) /* Disable */#define NFCONF_FCTRL_EN  FInsrt(0x1, fNFCONF_FCTRL) /* Enable */#define NFSTAT_RnB      (1 << 0)#define NFSTAT_nFWE     (1 << 8)#define NFSTAT_nFRE     (1 << 9)#define NFSTAT_ALE      (1 << 10)#define NFSTAT_CLE      (1 << 11)#define NFSTAT_AUTOBOOT (1 << 15)/* ADC and Touch Screen Interface */#define ADC_CTL_BASE		0x58000000#define bADC_CTL(Nb)		__REG(ADC_CTL_BASE + (Nb))/* Offset */#define oADCCON			0x00	/* R/W, ADC control register */#define oADCTSC			0x04	/* R/W, ADC touch screen ctl reg */#define oADCDLY			0x08	/* R/W, ADC start or interval delay reg */#define oADCDAT0		0x0c	/* R  , ADC conversion data reg */#define oADCDAT1		0x10	/* R  , ADC conversion data reg *//* Registers */#define ADCCON			bADC_CTL(oADCCON)#define ADCTSC			bADC_CTL(oADCTSC)#define ADCDLY			bADC_CTL(oADCDLY)#define ADCDAT0			bADC_CTL(oADCDAT0)#define ADCDAT1			bADC_CTL(oADCDAT1)/* Field */#define fADCCON_PRSCVL		Fld(8, 6)#define fADCCON_INPUT		Fld(3, 3)#define fTSC_XY_PST		Fld(2, 0)#define fADC_DELAY		Fld(6, 0)#define fDAT_UPDOWN		Fld(1, 15)#define fDAT_AUTO_PST		Fld(1, 14)#define fDAT_XY_PST		Fld(2, 12)#define fDAT_XPDATA		Fld(10, 0)#define fDAT_YPDATA		Fld(10, 0)/* ... */#define ADC_IN0                 0#define ADC_IN1                 1#define ADC_IN2                 2#define ADC_IN3                 3#define ADC_IN4                 4#define ADC_IN5                 5#define ADC_IN6                 6#define ADC_IN7                 7#define ADC_BUSY		1#define ADC_READY		0#define NOP_MODE		0#define X_AXIS_MODE		1#define Y_AXIS_MODE		2#define WAIT_INT_MODE		3/* ... */#define ADCCON_ECFLG		(1 << 15)#define PRESCALE_ENDIS		(1 << 14)#define PRESCALE_DIS		(PRESCALE_ENDIS*0)#define PRESCALE_EN		(PRESCALE_ENDIS*1)#if 0#define PRSCVL(x)		({ FClrFld(ADCCON, fADCCON_PRSCVL); \				   FInsrt((x), fADCCON_PRSCVL); })#define ADC_INPUT(x)		({ FClrFld(ADCCON, fADCCON_INPUT); \				   FInsrt((x), fADCCON_INPUT); })#endif#define PRSCVL(x)		(x << 6)#define ADC_INPUT(x)		(x << 3)#define ADCCON_STDBM		(1 << 2)        /* 1: standby mode, 0: normal mode */#define ADC_NORMAL_MODE		FClrBit(ADCCON, ADCCON_STDBM)#define ADC_STANDBY_MODE	(ADCCON_STDBM*1)#define ADCCON_READ_START	(1 << 1)#define ADC_START_BY_RD_DIS	FClrBit(ADCCON, ADCCON_READ_START)#define ADC_START_BY_RD_EN	(ADCCON_READ_START*1)#define ADC_START		(1 << 0)#define UD_SEN			(1 << 8)#define DOWN_INT		(UD_SEN*0)#define UP_INT			(UD_SEN*1)#define YM_SEN			(1 << 7)#define YM_HIZ			(YM_SEN*0)#define YM_GND			(YM_SEN*1)#define YP_SEN			(1 << 6)#define YP_EXTVLT		(YP_SEN*0)#define YP_AIN			(YP_SEN*1)#define XM_SEN			(1 << 5)#define XM_HIZ			(XM_SEN*0)#define XM_GND			(XM_SEN*1)#define XP_SEN			(1 << 4)#define XP_EXTVLT		(XP_SEN*0)#define XP_AIN			(XP_SEN*1)#define XP_PULL_UP		(1 << 3)#define XP_PULL_UP_EN		(XP_PULL_UP*0)#define XP_PULL_UP_DIS		(XP_PULL_UP*1)#define AUTO_PST		(1 << 2)#define CONVERT_MAN		(AUTO_PST*0)#define CONVERT_AUTO		(AUTO_PST*1)#define XP_PST(x)		(x << 0)/* DMA */#define DMA_CTL_BASE	0x4b000000#define bDMA_CTL(Nb,x)	__REG(DMA_CTL_BASE + (0x40*Nb) + (x))/* DMA channel 0 */#define DISRC0			bDMA_CTL(0, 0x00)#define DISRCC0			bDMA_CTL(0, 0x04)#define DIDST0			bDMA_CTL(0, 0x08)#define DIDSTC0			bDMA_CTL(0, 0x0c)#define DCON0			bDMA_CTL(0, 0x10)#define DSTAT0			bDMA_CTL(0, 0x14)#define DCSRC0			bDMA_CTL(0, 0x18)#define DCDST0			bDMA_CTL(0, 0x1c)#define DMTRIG0			bDMA_CTL(0, 0x20)/* DMA channel 1 */#define DISRC1			bDMA_CTL(1, 0x00)#define DISRCC1			bDMA_CTL(1, 0x04)#define DIDST1			bDMA_CTL(1, 0x08)#define DIDSTC1			bDMA_CTL(1, 0x0c)#define DCON1			bDMA_CTL(1, 0x10)#define DSTAT1			bDMA_CTL(1, 0x14)#define DCSRC1			bDMA_CTL(1, 0x18)#define DCDST1			bDMA_CTL(1, 0x1c)#define DMTRIG1			bDMA_CTL(1, 0x20)/* DMA channel 2 */#define DISRC2			bDMA_CTL(2, 0x00)#define DISRCC2			bDMA_CTL(2, 0x04)#define DIDST2			bDMA_CTL(2, 0x08)#define DIDSTC2			bDMA_CTL(2, 0x0c)#define DCON2			bDMA_CTL(2, 0x10)#define DSTAT2			bDMA_CTL(2, 0x14)#define DCSRC2			bDMA_CTL(2, 0x18)#define DCDST2			bDMA_CTL(2, 0x1c)#define DMTRIG2			bDMA_CTL(2, 0x20)/* DMA channel 3 */#define DISRC3			bDMA_CTL(3, 0x00)#define DISRCC3			bDMA_CTL(3, 0x04)#define DIDST3			bDMA_CTL(3, 0x08)#define DIDSTC3			bDMA_CTL(3, 0x0c)#define DCON3			bDMA_CTL(3, 0x10)#define DSTAT3			bDMA_CTL(3, 0x14)#define DCSRC3			bDMA_CTL(3, 0x18)#define DCDST3			bDMA_CTL(3, 0x1c)#define DMTRIG3			bDMA_CTL(3, 0x20)/* DISRC, DIDST Control registers */#define fDMA_BASE_ADDR		Fld(30, 0)      /* base address of src/dst data */#define DMA_BASE_ADDR(x)	FInsrt(x, fDMA_BASE_ADDR)#define LOC_SRC			(1 << 1)	/* select the location of source */#define ON_AHB			(LOC_SRC*0)#define ON_APB			(LOC_SRC*1)#define ADDR_MODE		(1 << 0)       /* select the address increment */#define ADDR_INC		(ADDR_MODE*0)#define ADDR_FIX		(ADDR_MODE*1)/* DCON Definitions */#define DCON_MODE		(1 << 31)	/* 0: demand, 1: handshake */#define DEMAND_MODE		(DCON_MODE*0)#define HS_MODE			(DCON_MODE*1)#define DCON_SYNC		(1 << 30)       /* sync to 0:PCLK, 1:HCLK */#define SYNC_PCLK		(DCON_SYNC*0)#define SYNC_HCLK		(DCON_SYNC*1)#define DCON_INT		(1 << 29)#define POLLING_MODE		(DCON_INT*0)#define INT_MODE		(DCON_INT*1)#define DCON_TSZ		(1 << 28)	/* tx size 0: a unit, 1: burst */#define TSZ_UNIT		(DCON_TSZ*0)#define TSZ_BURST		(DCON_TSZ*1)#define DCON_SERVMODE		(1 << 27)	/* 0: single, 1: whole service */#define SINGLE_SERVICE		(DCON_SERVMODE*0)#define WHOLE_SERVICE		(DCON_SERVMODE*1)#define fDCON_HWSRC		Fld(3, 24)	/* select request source */#define CH0_nXDREQ0		0#define CH0_UART0		1#define CH0_MMC			2#define CH0_TIMER		3#define CH0_USBEP1		4#define CH1_nXDREQ1		0#define CH1_UART1		1#define CH1_I2SSDI		2#define CH1_SPI			3#define CH1_USBEP2		4#define CH2_I2SSDO		0#define CH2_I2SSDI		1#define CH2_MMC			2#define CH2_TIMER		3#define CH2_USBEP3		4#define CH3_UART2		0#define CH3_MMC			1#define CH3_SPI			2#define CH3_TIMER		3#define CH3_USBEP4		4#define HWSRC(x)		FInsrt(x, fDCON_HWSRC)#define DCON_SWHW_SEL		(1 << 23)	/* DMA src 0: s/w 1: h/w */#define DMA_SRC_SW		(DCON_SWHW_SEL*0)#define DMA_SRC_HW		(DCON_SWHW_SEL*1)#define DCON_RELOAD		(1 << 22)	/* set auto-reload */#define SET_ATRELOAD		(DCON_RELOAD*0)#define CLR_ATRELOAD		(DCON_RELOAD*1)#define fDCON_DSZ		Fld(2, 20)#define DSZ_BYTE		0#define DSZ_HALFWORD		1#define DSZ_WORD		2#define DSZ(x)			FInsrt(x, fDCON_DSZ)#define readDSZ(x)		FExtr(x, fDCON_DSZ)#define fDCON_TC		Fld(20,0)#define TX_CNT(x)		FInsrt(x, fDCON_TC)/* STATUS Register Definitions  */#define fDSTAT_ST		Fld(2,20)	/* Status of DMA Controller */#define fDSTAT_TC		Fld(20,0)	/* Current value of transfer count */#define DMA_STATUS(chan)	FExtr((DSTAT0 + (0x20 * chan)), fDSTAT_ST)#define DMA_BUSY		(1 << 0)#define DMA_READY		(0 << 0)#define DMA_CURR_TC(chan)	FExtr((DSTAT0 + (0x20 * chan)), fDSTAT_TC)      /* DMA Trigger Register Definitions */#define DMASKTRIG_STOP		(1 << 2)	/* Stop the DMA operation */#define DMA_STOP		(DMASKTRIG_STOP*1)#define DMA_STOP_CLR		(DMASKTRIG_STOP*0)#define DMASKTRIG_ONOFF		(1 << 1)	/* DMA channel on/off */#define CHANNEL_ON		(DMASKTRIG_ONOFF*1)#define CHANNEL_OFF		(DMASKTRIG_ONOFF*0)#define DMASKTRIG_SW		(1 << 0)	/* Trigger DMA ch. in S/W req. mode */#define DMA_SW_REQ_CLR		(DMASKTRIG_SW*0)#define DMA_SW_REQ		(DMASKTRIG_SW*1)/* IIS Bus Interface */#define IIS_CTL_BASE		0x55000000#define bIIS_CTL(Nb)		__REG(IIS_CTL_BASE + (Nb))#define IISCON			bIIS_CTL(0x00)#define IISMOD			bIIS_CTL(0x04)#define IISPSR			bIIS_CTL(0x08)#define IISFIFOC		bIIS_CTL(0x0c)#define IISFIFOE		bIIS_CTL(0x10)#define IISCON_CH_RIGHT (1 << 8)        /* Right channel */#define IISCON_CH_LEFT  (0 << 8)        /* Left channel */#define IISCON_TX_RDY   (1 << 7)        /* Transmit FIFO is ready(not empty) */#define IISCON_RX_RDY   (1 << 6)        /* Receive FIFO is ready (not full) */#define IISCON_TX_DMA   (1 << 5)        /* Transmit DMA service reqeust */#define IISCON_RX_DMA   (1 << 4)        /* Receive DMA service reqeust */#define IISCON_TX_IDLE  (1 << 3)        /* Transmit Channel idle */#define IISCON_RX_IDLE  (1 << 2)        /* Receive Channel idle */#define IISCON_PRESCALE (1 << 1)        /* IIS Prescaler Enable */#define IISCON_EN       (1 << 0)        /* IIS enable(start) */#define IISMOD_SEL_MA   (0 << 8)        /* Master mode					                                              (IISLRCK, IISCLK are Output) */#define IISMOD_SEL_SL   (1 << 8)        /* Slave mode					                                              (IISLRCK, IISCLK are Input) */#define fIISMOD_SEL_TR  Fld(2, 6)       /* Transmit/Receive mode */#define IISMOD_SEL_TR   FMsk(fIISMOD_SEL_TR)#define IISMOD_SEL_NO   FInsrt(0x0, fIISMOD_SEL_TR)     /* No Transfer */#define IISMOD_SEL_RX   FInsrt(0x1, fIISMOD_SEL_TR)     /* Receive */#define IISMOD_SEL_TX   FInsrt(0x2, fIISMOD_SEL_TR)     /* Transmit */#define IISMOD_SEL_BOTH FInsrt(0x3, fIISMOD_SEL_TR)     /* Tx & Rx */#define IISMOD_CH_RIGHT (0 << 5)        /* high for right channel */#define IISMOD_CH_LEFT  (1 << 5)        /* high for left channel */#define IISMOD_FMT_IIS  (0 << 4)        /* IIS-compatible format */#define IISMOD_FMT_MSB  (1 << 4)        /* MSB(left)-justified format */#define IISMOD_BIT_8    (0 << 3)        /* Serial data bit/channel is 8 bit*/#define IISMOD_BIT_16   (1 << 3)        /* Serial data bit/channel is 16 bit*/#define IISMOD_FREQ_256 (0 << 2)        /* Master clock freq = 256 fs */#define IISMOD_FREQ_384 (1 << 2)        /* Master clock freq =