/****************************************************************************
* Copyright (c) 2002 Windond Electronics Corp.
* All rights reserved.
*
* FILE NAME: board.h
*
* DESCRIPTION: Board Specific Routines for W90N740.
*
* AUTHOR: Jen-Hao Tsai, PC30
****************************************************************************/
#ifndef _BOARD_H
#define _BOARD_H

#define S8    signed char
#define S16   signed short
#define S32   signed int
#define U8    unsigned char
#define U16   unsigned short
#define U32   unsigned int
#define REG8  volatile unsigned char
#define REG16 volatile unsigned short
#define REG32 volatile unsigned int
#define BYTE  U8

typedef char           int8;
typedef unsigned char  uint8;
typedef short          int16;
typedef unsigned short uint16;
typedef int            int32;
typedef unsigned int   uint32;

#define USHORT_MAX 65535  // maximum value of uint16 variable.

#ifndef NULL
#define NULL 0
#endif


// ASIC Address Definition
#define VPint   *(volatile unsigned int *)
#define VPshort *(volatile unsigned short *)
#define VPchar  *(volatile unsigned char *)


#define Base_Addr 0xfff00000
#define MacReg(num,x) (VPint(0xfff03000+num*0x800+x*0x4))
#define MacReg_DD(num,x) (VPint(0xfff03200+num*0x800+x*0x4))


// System Manager Control Registers
#define PDID   (VPint(Base_Addr+0x0000))
#define ARBCON (VPint(Base_Addr+0x0004))
#define PLLCON (VPint(Base_Addr+0x0008))
#define CLKSEL (VPint(Base_Addr+0x000c))


// Advanced Interrupt Controller Registers
#define AIC_SCR_EMC0   (VPint(Base_Addr+0x0008202c))
#define AIC_SCR_EMC1   (VPint(Base_Addr+0x00082030))
#define AIC_SCR_EMCTX0 (VPint(Base_Addr+0x00082034))
#define AIC_SCR_EMCTX1 (VPint(Base_Addr+0x00082038))
#define AIC_SCR_EMCRX0 (VPint(Base_Addr+0x0008203c))
#define AIC_SCR_EMCRX1 (VPint(Base_Addr+0x00082040))
#define AIC_SCR_TIMER0 (VPint(Base_Addr+0x0008201C))
#define AIC_SCR_TIMER1 (VPint(Base_Addr+0x00082020))
#define AIC_IRSR       (VPint(Base_Addr+0x00082100))
#define AIC_IASR       (VPint(Base_Addr+0x00082104))
#define AIC_ISR        (VPint(Base_Addr+0x00082108))
#define AIC_IPER       (VPint(Base_Addr+0x0008210c))
#define AIC_ISNR       (VPint(Base_Addr+0x00082110))
#define AIC_IMR        (VPint(Base_Addr+0x00082114))
#define AIC_OISR       (VPint(Base_Addr+0x00082118))
#define AIC_MECR       (VPint(Base_Addr+0x00082120))
#define AIC_MDCR       (VPint(Base_Addr+0x00082124))
#define AIC_SSCR       (VPint(Base_Addr+0x00082128))
#define AIC_SCCR       (VPint(Base_Addr+0x0008212c))
#define AIC_EOSCR      (VPint(Base_Addr+0x00082130))
// MAC Interrupt Sources
#define EMCTXINT0 13
#define EMCTXINT1 14
#define EMCRXINT0 15
#define EMCRXINT1 16

//TIMER Interrupt Source
#define TIMERINT0 7
#define TIMERINT1 8

// Routines to Enable/Disable Interrupts
#define Enable_Int(n)     AIC_MECR = (1<<(n))
#define Disable_Int(n)    AIC_MDCR = (1<<(n))
#define Enable_Int_All()  AIC_MECR = 0xffff
#define Disable_Int_All() AIC_MDCR = 0xffff


// EMC 0 Control Registers
#define CAMCMR_0       (VPint(Base_Addr+0x3000))     // CAM Registers
#define CAMEN_0        (VPint(Base_Addr+0x3004))
#define CAM0M_Base_0   Base_Addr+0x3008
#define CAM0L_Base_0   Base_Addr+0x300c
#define CAMxM_Reg_0(x) (VPint(CAM0M_Base_0+x*0x8))
#define CAMxL_Reg_0(x) (VPint(CAM0L_Base_0+x*0x8))
#define MIEN_0         (VPint(Base_Addr+0x3088))     // MAC Registers
#define MCMDR_0        (VPint(Base_Addr+0x308c))
#define MIID_0         (VPint(Base_Addr+0x3090))
#define MIIDA_0        (VPint(Base_Addr+0x3094))
#define MPCNT_0        (VPint(Base_Addr+0x3098))
#define TXDLSA_0       (VPint(Base_Addr+0x309c))     // DMA Registers
#define RXDLSA_0       (VPint(Base_Addr+0x30a0))
#define DMARFC_0       (VPint(Base_Addr+0x30a4))
#define TSDR_0         (VPint(Base_Addr+0x30a8))
#define RSDR_0         (VPint(Base_Addr+0x30ac))
#define FIFOTHD_0      (VPint(Base_Addr+0x30b0))     // Test Registers
// EMC 0 Status Registers
#define MISTA_0        (VPint(Base_Addr+0x30b4))     // MAC Registers
#define MGSTA_0        (VPint(Base_Addr+0x30b8))
#define MRPC_0         (VPint(Base_Addr+0x30bc))
#define MRPCC_0        (VPint(Base_Addr+0x30c0))
#define MREPC_0        (VPint(Base_Addr+0x30c4))
#define DMARFS_0       (VPint(Base_Addr+0x30c8))     // DMA Registers
#define CTXDSA_0       (VPint(Base_Addr+0x30cc))
#define CTXBSA_0       (VPint(Base_Addr+0x30d0))
#define CRXDSA_0       (VPint(Base_Addr+0x30d4))
#define CRXBSA_0       (VPint(Base_Addr+0x30d8))
// EMC 0 Diagnostic Registers
#define TICS_0         (VPint(Base_Addr+0x3100))     // Test Registers
#define RXFSM_0        (VPint(Base_Addr+0x3200))     // Debug Registers
#define TXFSM_0        (VPint(Base_Addr+0x3204))
#define FSM0_0         (VPint(Base_Addr+0x3208))
#define FSM1_0         (VPint(Base_Addr+0x320c))
#define DCR_0          (VPint(Base_Addr+0x3210))
#define BISTR_0        (VPint(Base_Addr+0x3300))     // BIST Registers


// EMC 1 Control Registers
#define CAMCMR_1       (VPint(Base_Addr+0x3800))     // CAM Registers
#define CAMEN_1        (VPint(Base_Addr+0x3804))
#define CAM0M_Base_1   Base_Addr+0x3808
#define CAM0L_Base_1   Base_Addr+0x380c
#define CAMxM_Reg_1(x) (VPint(CAM0M_Base_1+x*0x8))
#define CAMxL_Reg_1(x) (VPint(CAM0L_Base_1+x*0x8))
#define MIEN_1         (VPint(Base_Addr+0x3888))     // MAC Registers
#define MCMDR_1        (VPint(Base_Addr+0x388c))
#define MIID_1         (VPint(Base_Addr+0x3890))
#define MIIDA_1        (VPint(Base_Addr+0x3894))
#define MPCNT_1        (VPint(Base_Addr+0x3898))
#define TXDLSA_1       (VPint(Base_Addr+0x389c))     // DMA Registers
#define RXDLSA_1       (VPint(Base_Addr+0x38a0))
#define DMARFC_1       (VPint(Base_Addr+0x38a4))
#define TSDR_1         (VPint(Base_Addr+0x38a8))
#define RSDR_1         (VPint(Base_Addr+0x38ac))
#define FIFOTHD_1      (VPint(Base_Addr+0x38b0))     // Test Registers
// EMC 0 Status Registers
#define MISTA_1        (VPint(Base_Addr+0x38b4))     // MAC Registers
#define MGSTA_1        (VPint(Base_Addr+0x38b8))
#define MRPC_1         (VPint(Base_Addr+0x38bc))
#define MRPCC_1        (VPint(Base_Addr+0x38c0))
#define MREPC_1        (VPint(Base_Addr+0x38c4))
#define DMARFS_1       (VPint(Base_Addr+0x38c8))     // DMA Registers
#define CTXDSA_1       (VPint(Base_Addr+0x38cc))
#define CTXBSA_1       (VPint(Base_Addr+0x38d0))
#define CRXDSA_1       (VPint(Base_Addr+0x38d4))
#define CRXBSA_1       (VPint(Base_Addr+0x38d8))
// EMC 0 Diagnostic Registers
#define TICS_1         (VPint(Base_Addr+0x3900))     // Test Registers
#define RXFSM_1        (VPint(Base_Addr+0x3a00))     // Debug Registers
#define TXFSM_1        (VPint(Base_Addr+0x3a04))
#define FSM0_1         (VPint(Base_Addr+0x3a08))
#define FSM1_1         (VPint(Base_Addr+0x3a0c))
#define DCR_1          (VPint(Base_Addr+0x3a10))
#define BISTR_1        (VPint(Base_Addr+0x3b00))     // BIST Registers


// Function Prototype for Interrupt
extern void IRQ_IntHandler(int x);
extern void SysSetInterrupt(REG32 vector, void (*)()) ;

#define USE_TIME //CMN
#endif