library ieee;                          --全成為38KHz的載波
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity zb is
 port(d,clk,key_en:in std_logic;
      zb1:out std_logic);
end;

architecture one of zb is
  signal c_c:std_logic;
 begin
   process(key_en)
   begin
     if key_en'event and key_en='1' then
         c_c<='1';
     end if;
   end process;

process(c_c,clk,d)
begin
   if c_c='1' then
    zb1<=clk and d;
   end if;
end process;

end;