;*******************************************************************************
; This code runs at the end of every frame of data transferred into the buffer
; from McBSP1 DRR11 (data receive register) by DMA Channel 2. At the end of the
; DMAC2 block, it sets up DMA Channel 3 to transfer the data from the buffer to
; DXR11 (data transmit register) of McBSP1.
;
; This code also calls the DSPlib function FIRS to process each frame of data
; in place. 
;
; Author: Scott Bland    Date: 03/21/2000
;*******************************************************************************


DMA_CH3_ELEM_CNT .set       100h
DMA_CH3_NUM_FRM  .set       1
DSYNC_REVT1      .set       0101b << 12
DMA3_CTR         .set       4141h
 
                 .global    _DMAC2ISR     						;global references
                 .global    _frame,_flag,_buffer				;_buffer is start addr of buffer
                 .global    _delaybuff,_firs,_delayptr1 		;buffer pointers 
                 .global	_TI_FIRS_COEFFS
                 .global    _brd_led_enable                     ;board LED on
                 .global    _brd_led_disable                    ;and off
                 .global    _currbuff, _first_frame,_temp       ;processing flags
			

                 .mmregs 

DMSA             .set    55h        ;Subbank Address Register
DMSDI            .set    56h        ;Subbank Access Register With Autoincrement
DXR11            .set    43h        ;McBSP1 data transmit register
DRR11            .set    41h        ;McBSP1 data receive register
DMGSA            .set    24h        ;global reload registers .. source addr
DMSRC3           .set    0Fh        ;Subbank address for DMA3 source address register
DMPREC           .set    54h        ;DMA control


                 .sect   "asmcode"
	
_DMAC2ISR   
        PSHM     ST0                ;save context
        PSHM     ST1
        PSHM     AL
        PSHM     AH
        PSHM     AG
        PSHM     AR4
        PSHM     AR5


;First, determine which input frame has been completed...
			

        STM		#_frame,AR4         ;AR4 holds address of frame count (initialized in .c file)
        ADDM	#1,*AR4             ;increment frame count (next input frame)
        CMPM	*AR4,#3             ;Frame 3 ?
        BC		frame3,TC           ;Frame 3
        CMPM	*AR4,#2             ;Frame 2 ?
        BC		frame2,TC           ;Frame 2
                                    ;else, it's Frame 1
			                        			                        
frame1:
        LD      #_buffer,A          ;A holds first argument ... address of buffer
        BITF    *(_flag), #0AAh     ;very first frame?
        BC      send_output, TC     ;No, send output frame and process this frame
        B       process             ;process this frame and return
			     

frame2:		
        LD      #_buffer+100h,A     ;A holds first argument ... address of buffer
        B       send_output         ;send output frame and process this frame
			

frame3:                             ;set frame back to zero
        ST      #0,*AR4             ;AR4 still holds address of frame count
        LD      #_buffer+200h,A  	;A holds first argument ... address of buffer  
        b       send_output         ;send output frame and process this frame


process:      
        STM	    #256,AR4            ;last parameter ... number of data elements
        PSHM    AR4
			
        STM     #8,AR4             ;number of coefficients
        PSHM    AR4
			
        STM     #_delayptr1,AR4     ;pointer to location of delay buffer
        PSHM    AR4
			
        STM     #0x100, T           ;load buffer size into T
        LD      #_buffer+0x400, B   ;load base address of second output
        MAS     *(#_currbuff), B    ;if current buffer is 0, B = #_buffer + 0x0400
                                    ;if current buffer is 1, B = #_buffer + 0x0300
        STLM    B, AR4
        NOP
        PSHM    AR4                 ;output buffer
			

                                    ;state of the switch
        STM     #_temp,AR4          ;AR4 points to temporary location
        PORTR   #1,*AR4             ;read the I/O port for the DIP switch
        BIT     *AR4,15-5           ;and test bit 5 (switch nearest reset switch)
        NOP                         ;extra pipeline cycle
        NOP
        NOP
        XC      2,NTC               ;either do or don't perform call based on the
        B       loopback            ;loopback the received frame
        
        CALL    _firs               ;call the DSPLIB FIRS function
        B       end_process         ;end of processing


loopback:                           ;digital loopback
        STLM    B, AR5              ;AR5 = output buffer address
        STLM    A, AR3              ;AR3 = input buffer address
        NOP
        RPT     #0xff
        MVDD    *AR3+, *AR5+
            

end_process:
        XORM    #1, *(#_currbuff)

        POPM    AR4                 ;stack restoration
        POPM    AR4
        POPM    AR4
        POPM    AR4
        ;POPM    AR4  
            
;Determine if this is the very first interrupt (if so, need a dummy write)

        STM     #_flag, AR5         ;AR5 holds address of flag (initialized in .c file)
        CMPM    *AR5, #0            ;Test flag=0
        BC      finish, NTC         ;if flag !=0, do nothing
        ST      #0AAh, *AR5         ;else, set flag to non-zero value
  			
finish:
        POPM    AR5            	    ;context restoration
        POPM    AR4
        POPM    AG
        POPM    AH
        POPM    AL
        POPM    ST1
        POPM    ST0 

        RETE


send_output:                                    ;this routine writes a processed buffer
                                                ;to the output
        BITF    *(DMPREC), #0008h               ;poll for DMA3 transfer complete
        BC      send_output, TC
            
        LD      #_buffer+0x300, B               ;compute address of output buffer to
        MAC     *(#_currbuff), #0x100, B        ;be used by DMA3 (processed data)
             
        STM     #DMSRC3,DMSA                    ;program DMA3 registers
        STLM    B ,DMSDI	                    ;source
        STM     #DXR11,DMSDI                    ;destination
        STM     #DMA_CH3_ELEM_CNT-1,DMSDI       ;element count
        STM     #(DMA_CH3_NUM_FRM-1) | DSYNC_REVT1, DMSDI         ;frame count 
        STM     #DMA3_CTR, DMSDI                ;DMA3 control
            			
        ORM     #0008h, *(DMPREC)               ;enable DMAC 3
        B       process                         ;go process just received buffer