;****************************************************************
;                       RS232 DEMO
;  Copyright (c) 2001 SJTU DSP Tech. Center. All Rights Reserved.
;  History:
;		Date		Authors			
;		2002/08/12	ChenShanrong		
;*****************************************************************

	.mmregs

	.include "uartasm.h54"

	.text
;************************************************
;Function: UART_Init
;Description:
;	Initialize uart chip TL16C550
;Input :
;	None
;Output:
;	None
;************************************************
var_reg		.set	0
off_m		.set	-1
off_p		.set	1

UART_Init:
	frame	off_m

	;reset  bit 4 in cntl2 to select UART as the signal source
	portr	ADDR_CNTL2, *SP(var_reg)
	andm	#0xffef, *SP(var_reg)
	portw	*SP(var_reg), ADDR_CNTL2


	;test for existance
	st	#0x55, *SP(var_reg)
	portw	*SP(var_reg), ADDR_SCR   ;write out
	portr	ADDR_SCR, *SP(var_reg)   ;read back
	ld	*SP(var_reg), A
	sub	#0x55, A, B              ;check for same
	bc	uart_no_error,  BEQ

	;if initial of rs232 meet with error, LED3 shines
	portr	ADDR_CNTL1, *SP(var_reg)
	orm	#0x04, *SP(var_reg)
	portw	*SP(var_reg), ADDR_CNTL1

	b	uart_init_exit


uart_no_error:
	;enable divisor latch(set DLAB) to set baud rate
	st	#0x83, *SP(var_reg)
	portw	*SP(var_reg), ADDR_LCR

	;set baud rate=9600
	st	#0x00, *SP(var_reg)
	portw	*SP(var_reg), ADDR_DIV_MSB	;write DLM(MSB)
	st	#0x18, *SP(var_reg)
	portw	*SP(var_reg), ADDR_DIV_LSB	;write DEC(LSB)

	;disable divisor latch (reset DKAB)
	st	#0x03, *SP(var_reg)
	portw	*SP(var_reg), ADDR_LCR

	;only receive interrupt
	st	#0x05, *SP(var_reg)
	portw	*SP(var_reg), ADDR_IER

	;set FCR
	st	#0x08, *SP(var_reg)
	portw	*SP(var_reg), ADDR_FCR

	;no loopback, no output
	st	#0x00, *SP(var_reg)
	portw	*SP(var_reg) ,ADDR_MCR

	;check LED1 and LED2, then both shut off
	portr	ADDR_CNTL1, *SP(var_reg)
	orm		#0x07, *SP(var_reg)
	portw	*SP(var_reg), ADDR_CNTL1

	;delay some time
	stm		#50, AR1
delay_out_loop:
	stm		#1000, BRC
	rptb	delay_inner_loop-1
	rpt 	#1000
	nop
delay_inner_loop:
	banz	delay_out_loop, *AR1-

	portr	ADDR_CNTL1, *SP(var_reg)
	andm	#0xF8, *SP(var_reg)
	portw	*SP(var_reg), ADDR_CNTL1

uart_init_exit:
	frame	#off_p
	ret

;end of uart_init.s54