/* *  linux/include/linux/mtd/nand.h * *  Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> *                     Steven J. Hill <sjhill@realitydiluted.com> *		       Thomas Gleixner <tglx@linutronix.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Info: *	Contains standard defines and IDs for NAND flash devices * * Changelog: *	See git changelog. */#ifndef __LINUX_MTD_NAND_H#define __LINUX_MTD_NAND_H/* XXX U-BOOT XXX */#if 0#include <linux/wait.h>#include <linux/spinlock.h>#include <linux/mtd/mtd.h>#endif#include "config.h"#include "linux/mtd/compat.h"#include "linux/mtd/mtd.h"#include "linux/mtd/bbm.h"struct mtd_info;/* Scan and identify a NAND device */extern int nand_scan (struct mtd_info *mtd, int max_chips);/* Separate phases of nand_scan(), allowing board driver to intervene * and override command or ECC setup according to flash type */extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);extern int nand_scan_tail(struct mtd_info *mtd);/* Free resources held by the NAND device */extern void nand_release (struct mtd_info *mtd);/* Internal helper for board drivers which need to override command function */extern void nand_wait_ready(struct mtd_info *mtd);/* This constant declares the max. oobsize / page, which * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */#define NAND_MAX_OOBSIZE	128#define NAND_MAX_PAGESIZE	4096/* * Constants for hardware specific CLE/ALE/NCE function * * These are bits which can be or'ed to set/clear multiple * bits in one go. *//* Select the chip by setting nCE to low */#define NAND_NCE		0x01/* Select the command latch by setting CLE to high */#define NAND_CLE		0x02/* Select the address latch by setting ALE to high */#define NAND_ALE		0x04#define NAND_CTRL_CLE		(NAND_NCE | NAND_CLE)#define NAND_CTRL_ALE		(NAND_NCE | NAND_ALE)#define NAND_CTRL_CHANGE	0x80/* * Standard NAND flash commands */#define NAND_CMD_READ0		0#define NAND_CMD_READ1		1#define NAND_CMD_RNDOUT		5#define NAND_CMD_PAGEPROG	0x10#define NAND_CMD_READOOB	0x50#define NAND_CMD_ERASE1		0x60#define NAND_CMD_STATUS		0x70#define NAND_CMD_STATUS_MULTI	0x71#define NAND_CMD_SEQIN		0x80#define NAND_CMD_RNDIN		0x85#define NAND_CMD_READID		0x90#define NAND_CMD_ERASE2		0xd0#define NAND_CMD_RESET		0xff/* Extended commands for large page devices */#define NAND_CMD_READSTART	0x30#define NAND_CMD_RNDOUTSTART	0xE0#define NAND_CMD_CACHEDPROG	0x15/* Extended commands for AG-AND device *//* * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but *       there is no way to distinguish that from NAND_CMD_READ0 *       until the remaining sequence of commands has been completed *       so add a high order bit and mask it off in the command. */#define NAND_CMD_DEPLETE1	0x100#define NAND_CMD_DEPLETE2	0x38#define NAND_CMD_STATUS_MULTI	0x71#define NAND_CMD_STATUS_ERROR	0x72/* multi-bank error status (banks 0-3) */#define NAND_CMD_STATUS_ERROR0	0x73#define NAND_CMD_STATUS_ERROR1	0x74#define NAND_CMD_STATUS_ERROR2	0x75#define NAND_CMD_STATUS_ERROR3	0x76#define NAND_CMD_STATUS_RESET	0x7f#define NAND_CMD_STATUS_CLEAR	0xff#define NAND_CMD_NONE		-1/* Status bits */#define NAND_STATUS_FAIL	0x01#define NAND_STATUS_FAIL_N1	0x02#define NAND_STATUS_TRUE_READY	0x20#define NAND_STATUS_READY	0x40#define NAND_STATUS_WP		0x80/* * Constants for ECC_MODES */typedef enum {	NAND_ECC_NONE,	NAND_ECC_SOFT,	NAND_ECC_HW,	NAND_ECC_HW_SYNDROME,} nand_ecc_modes_t;/* * Constants for Hardware ECC *//* Reset Hardware ECC for read */#define NAND_ECC_READ		0/* Reset Hardware ECC for write */#define NAND_ECC_WRITE		1/* Enable Hardware ECC before syndrom is read back from flash */#define NAND_ECC_READSYN	2/* Bit mask for flags passed to do_nand_read_ecc */#define NAND_GET_DEVICE		0x80/* Option constants for bizarre disfunctionality and real*  features*//* Chip can not auto increment pages */#define NAND_NO_AUTOINCR	0x00000001/* Buswitdh is 16 bit */#define NAND_BUSWIDTH_16	0x00000002/* Device supports partial programming without padding */#define NAND_NO_PADDING		0x00000004/* Chip has cache program function */#define NAND_CACHEPRG		0x00000008/* Chip has copy back function */#define NAND_COPYBACK		0x00000010/* AND Chip which has 4 banks and a confusing page / block * assignment. See Renesas datasheet for further information */#define NAND_IS_AND		0x00000020/* Chip has a array of 4 pages which can be read without * additional ready /busy waits */#define NAND_4PAGE_ARRAY	0x00000040/* Chip requires that BBT is periodically rewritten to prevent * bits from adjacent blocks from 'leaking' in altering data. * This happens with the Renesas AG-AND chips, possibly others.  */#define BBT_AUTO_REFRESH	0x00000080/* Chip does not require ready check on read. True * for all large page devices, as they do not support * autoincrement.*/#define NAND_NO_READRDY		0x00000100/* Chip does not allow subpage writes */#define NAND_NO_SUBPAGE_WRITE	0x00000200/* Options valid for Samsung large page devices */#define NAND_SAMSUNG_LP_OPTIONS \	(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)/* Macros to identify the above */#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))/* Large page NAND with SOFT_ECC should support subpage reads */#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \					&& (chip->page_shift > 9))/* Mask to zero out the chip options, which come from the id table */#define NAND_CHIPOPTIONS_MSK	(0x0000ffff & ~NAND_NO_AUTOINCR)/* Non chip related options *//* Use a flash based bad block table. This option is passed to the * default bad block table function. */#define NAND_USE_FLASH_BBT	0x00010000/* This option skips the bbt scan during initialization. */#define NAND_SKIP_BBTSCAN	0x00020000/* This option is defined if the board driver allocates its own buffers   (e.g. because it needs them DMA-coherent */#define NAND_OWN_BUFFERS	0x00040000/* Options set by nand scan *//* bbt has already been read */#define NAND_BBT_SCANNED	0x40000000/* Nand scan has allocated controller struct */#define NAND_CONTROLLER_ALLOC	0x80000000/* Cell info constants */#define NAND_CI_CHIPNR_MSK	0x03#define NAND_CI_CELLTYPE_MSK	0x0C/* Keep gcc happy */struct nand_chip;/** * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices * @lock:               protection lock * @active:		the mtd device which holds the controller currently * @wq:			wait queue to sleep on if a NAND operation is in progress *                      used instead of the per chip wait queue when a hw controller is available */struct nand_hw_control {/* XXX U-BOOT XXX */#if 0	spinlock_t	 lock;	wait_queue_head_t wq;#endif	struct nand_chip *active;};/** * struct nand_ecc_ctrl - Control structure for ecc * @mode:	ecc mode * @steps:	number of ecc steps per page * @size:	data bytes per ecc step * @bytes:	ecc bytes per step * @total:	total number of ecc bytes per page * @prepad:	padding information for syndrome based ecc generators * @postpad:	padding information for syndrome based ecc generators * @layout:	ECC layout control struct pointer * @hwctl:	function to control hardware ecc generator. Must only *		be provided if an hardware ECC is available * @calculate:	function for ecc calculation or readback from ecc hardware * @correct:	function for ecc correction, matching to ecc generator (sw/hw) * @read_page_raw:	function to read a raw page without ECC * @write_page_raw:	function to write a raw page without ECC * @read_page:	function to read a page according to the ecc generator requirements * @write_page:	function to write a page according to the ecc generator requirements * @read_oob:	function to read chip OOB data * @write_oob:	function to write chip OOB data */struct nand_ecc_ctrl {	nand_ecc_modes_t	mode;	int			steps;	int			size;	int			bytes;	int			total;	int			prepad;	int			postpad;	struct nand_ecclayout	*layout;	void			(*hwctl)(struct mtd_info *mtd, int mode);	int			(*calculate)(struct mtd_info *mtd,					     const uint8_t *dat,					     uint8_t *ecc_code);	int			(*correct)(struct mtd_info *mtd, uint8_t *dat,					   uint8_t *read_ecc,					   uint8_t *calc_ecc);	int			(*read_page_raw)(struct mtd_info *mtd,						 struct nand_chip *chip,						 uint8_t *buf);	void			(*write_page_raw)(struct mtd_info *mtd,						  struct nand_chip *chip,						  const uint8_t *buf);	int			(*read_page)(struct mtd_info *mtd,					     struct nand_chip *chip,					     uint8_t *buf);