/* * (C) Copyright 2006-2008 * Texas Instruments, <www.ti.com> * Syed Mohammed Khasim <x0khasim@ti.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef _MUX_H_#define _MUX_H_/* * IEN  - Input Enable * IDIS - Input Disable * PTD  - Pull type Down * PTU  - Pull type Up * DIS  - Pull type selection is inactive * EN   - Pull type selection is active * M0   - Mode 0 */#define IEN	(1 << 8)#define IDIS	(0 << 8)#define PTU	(1 << 4)#define PTD	(0 << 4)#define EN	(1 << 3)#define DIS	(0 << 3)#define M0	0#define M1	1#define M2	2#define M3	3#define M4	4#define M5	5#define M6	6#define M7	7/* * To get the actual address the offset has to added * with OMAP34XX_CTRL_BASE to get the actual address *//*SDRC*/#define CONTROL_PADCONF_SDRC_D0		0x0030#define CONTROL_PADCONF_SDRC_D1		0x0032#define CONTROL_PADCONF_SDRC_D2		0x0034#define CONTROL_PADCONF_SDRC_D3		0x0036#define CONTROL_PADCONF_SDRC_D4		0x0038#define CONTROL_PADCONF_SDRC_D5		0x003A#define CONTROL_PADCONF_SDRC_D6		0x003C#define CONTROL_PADCONF_SDRC_D7		0x003E#define CONTROL_PADCONF_SDRC_D8		0x0040#define CONTROL_PADCONF_SDRC_D9		0x0042#define CONTROL_PADCONF_SDRC_D10	0x0044#define CONTROL_PADCONF_SDRC_D11	0x0046#define CONTROL_PADCONF_SDRC_D12	0x0048#define CONTROL_PADCONF_SDRC_D13	0x004A#define CONTROL_PADCONF_SDRC_D14	0x004C#define CONTROL_PADCONF_SDRC_D15	0x004E#define CONTROL_PADCONF_SDRC_D16	0x0050#define CONTROL_PADCONF_SDRC_D17	0x0052#define CONTROL_PADCONF_SDRC_D18	0x0054#define CONTROL_PADCONF_SDRC_D19	0x0056#define CONTROL_PADCONF_SDRC_D20	0x0058#define CONTROL_PADCONF_SDRC_D21	0x005A#define CONTROL_PADCONF_SDRC_D22	0x005C#define CONTROL_PADCONF_SDRC_D23	0x005E#define CONTROL_PADCONF_SDRC_D24	0x0060#define CONTROL_PADCONF_SDRC_D25	0x0062#define CONTROL_PADCONF_SDRC_D26	0x0064#define CONTROL_PADCONF_SDRC_D27	0x0066#define CONTROL_PADCONF_SDRC_D28	0x0068#define CONTROL_PADCONF_SDRC_D29	0x006A#define CONTROL_PADCONF_SDRC_D30	0x006C#define CONTROL_PADCONF_SDRC_D31	0x006E#define CONTROL_PADCONF_SDRC_CLK	0x0070#define CONTROL_PADCONF_SDRC_DQS0	0x0072#define CONTROL_PADCONF_SDRC_DQS1	0x0074#define CONTROL_PADCONF_SDRC_DQS2	0x0076#define CONTROL_PADCONF_SDRC_DQS3	0x0078/*GPMC*/#define CONTROL_PADCONF_GPMC_A1		0x007A#define CONTROL_PADCONF_GPMC_A2		0x007C#define CONTROL_PADCONF_GPMC_A3		0x007E#define CONTROL_PADCONF_GPMC_A4		0x0080#define CONTROL_PADCONF_GPMC_A5		0x0082#define CONTROL_PADCONF_GPMC_A6		0x0084#define CONTROL_PADCONF_GPMC_A7		0x0086#define CONTROL_PADCONF_GPMC_A8		0x0088#define CONTROL_PADCONF_GPMC_A9		0x008A#define CONTROL_PADCONF_GPMC_A10	0x008C#define CONTROL_PADCONF_GPMC_D0		0x008E#define CONTROL_PADCONF_GPMC_D1		0x0090#define CONTROL_PADCONF_GPMC_D2		0x0092#define CONTROL_PADCONF_GPMC_D3		0x0094#define CONTROL_PADCONF_GPMC_D4		0x0096#define CONTROL_PADCONF_GPMC_D5		0x0098#define CONTROL_PADCONF_GPMC_D6		0x009A#define CONTROL_PADCONF_GPMC_D7		0x009C#define CONTROL_PADCONF_GPMC_D8		0x009E#define CONTROL_PADCONF_GPMC_D9		0x00A0#define CONTROL_PADCONF_GPMC_D10	0x00A2#define CONTROL_PADCONF_GPMC_D11	0x00A4#define CONTROL_PADCONF_GPMC_D12	0x00A6#define CONTROL_PADCONF_GPMC_D13	0x00A8#define CONTROL_PADCONF_GPMC_D14	0x00AA#define CONTROL_PADCONF_GPMC_D15	0x00AC#define CONTROL_PADCONF_GPMC_NCS0	0x00AE#define CONTROL_PADCONF_GPMC_NCS1	0x00B0#define CONTROL_PADCONF_GPMC_NCS2	0x00B2#define CONTROL_PADCONF_GPMC_NCS3	0x00B4#define CONTROL_PADCONF_GPMC_NCS4	0x00B6#define CONTROL_PADCONF_GPMC_NCS5	0x00B8#define CONTROL_PADCONF_GPMC_NCS6	0x00BA#define CONTROL_PADCONF_GPMC_NCS7	0x00BC#define CONTROL_PADCONF_GPMC_CLK	0x00BE#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0#define CONTROL_PADCONF_GPMC_NOE	0x00C2#define CONTROL_PADCONF_GPMC_NWE	0x00C4#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6#define CONTROL_PADCONF_GPMC_NBE1	0x00C8#define CONTROL_PADCONF_GPMC_NWP	0x00CA#define CONTROL_PADCONF_GPMC_WAIT0	0x00CC#define CONTROL_PADCONF_GPMC_WAIT1	0x00CE#define CONTROL_PADCONF_GPMC_WAIT2	0x00D0#define CONTROL_PADCONF_GPMC_WAIT3	0x00D2/*DSS*/#define CONTROL_PADCONF_DSS_PCLK	0x00D4#define CONTROL_PADCONF_DSS_HSYNC	0x00D6#define CONTROL_PADCONF_DSS_VSYNC	0x00D8#define CONTROL_PADCONF_DSS_ACBIAS	0x00DA#define CONTROL_PADCONF_DSS_DATA0	0x00DC#define CONTROL_PADCONF_DSS_DATA1	0x00DE#define CONTROL_PADCONF_DSS_DATA2	0x00E0#define CONTROL_PADCONF_DSS_DATA3	0x00E2#define CONTROL_PADCONF_DSS_DATA4	0x00E4#define CONTROL_PADCONF_DSS_DATA5	0x00E6#define CONTROL_PADCONF_DSS_DATA6	0x00E8#define CONTROL_PADCONF_DSS_DATA7	0x00EA#define CONTROL_PADCONF_DSS_DATA8	0x00EC#define CONTROL_PADCONF_DSS_DATA9	0x00EE#define CONTROL_PADCONF_DSS_DATA10	0x00F0#define CONTROL_PADCONF_DSS_DATA11	0x00F2#define CONTROL_PADCONF_DSS_DATA12	0x00F4#define CONTROL_PADCONF_DSS_DATA13	0x00F6#define CONTROL_PADCONF_DSS_DATA14	0x00F8#define CONTROL_PADCONF_DSS_DATA15	0x00FA#define CONTROL_PADCONF_DSS_DATA16	0x00FC#define CONTROL_PADCONF_DSS_DATA17	0x00FE#define CONTROL_PADCONF_DSS_DATA18	0x0100#define CONTROL_PADCONF_DSS_DATA19	0x0102#define CONTROL_PADCONF_DSS_DATA20	0x0104#define CONTROL_PADCONF_DSS_DATA21	0x0106#define CONTROL_PADCONF_DSS_DATA22	0x0108#define CONTROL_PADCONF_DSS_DATA23	0x010A/*CAMERA*/#define CONTROL_PADCONF_CAM_HS		0x010C#define CONTROL_PADCONF_CAM_VS		0x010E#define CONTROL_PADCONF_CAM_XCLKA	0x0110#define CONTROL_PADCONF_CAM_PCLK	0x0112#define CONTROL_PADCONF_CAM_FLD		0x0114#define CONTROL_PADCONF_CAM_D0		0x0116#define CONTROL_PADCONF_CAM_D1		0x0118#define CONTROL_PADCONF_CAM_D2		0x011A#define CONTROL_PADCONF_CAM_D3		0x011C#define CONTROL_PADCONF_CAM_D4		0x011E#define CONTROL_PADCONF_CAM_D5		0x0120#define CONTROL_PADCONF_CAM_D6		0x0122#define CONTROL_PADCONF_CAM_D7		0x0124#define CONTROL_PADCONF_CAM_D8		0x0126#define CONTROL_PADCONF_CAM_D9		0x0128#define CONTROL_PADCONF_CAM_D10		0x012A#define CONTROL_PADCONF_CAM_D11		0x012C#define CONTROL_PADCONF_CAM_XCLKB	0x012E#define CONTROL_PADCONF_CAM_WEN		0x0130#define CONTROL_PADCONF_CAM_STROBE	0x0132#define CONTROL_PADCONF_CSI2_DX0	0x0134#define CONTROL_PADCONF_CSI2_DY0	0x0136#define CONTROL_PADCONF_CSI2_DX1	0x0138#define CONTROL_PADCONF_CSI2_DY1	0x013A/*Audio Interface */#define CONTROL_PADCONF_MCBSP2_FSX	0x013C#define CONTROL_PADCONF_MCBSP2_CLKX	0x013E#define CONTROL_PADCONF_MCBSP2_DR	0x0140#define CONTROL_PADCONF_MCBSP2_DX	0x0142#define CONTROL_PADCONF_MMC1_CLK	0x0144#define CONTROL_PADCONF_MMC1_CMD	0x0146#define CONTROL_PADCONF_MMC1_DAT0	0x0148#define CONTROL_PADCONF_MMC1_DAT1	0x014A#define CONTROL_PADCONF_MMC1_DAT2	0x014C#define CONTROL_PADCONF_MMC1_DAT3	0x014E#define CONTROL_PADCONF_MMC1_DAT4	0x0150#define CONTROL_PADCONF_MMC1_DAT5	0x0152#define CONTROL_PADCONF_MMC1_DAT6	0x0154