/* * (C) Copyright 2003 * AT91RM9200 definitions * Author : ATMEL AT91 application group * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef AT91RM9200_H#define AT91RM9200_H#ifndef __ASSEMBLY__typedef volatile unsigned int AT91_REG;		/* Hardware register definition *//*****************************************************************************//*        SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface       *//*****************************************************************************/typedef struct _AT91S_TC{	AT91_REG	 TC_CCR;	/* Channel Control Register */	AT91_REG	 TC_CMR;	/* Channel Mode Register */	AT91_REG	 Reserved0[2];	/*  */	AT91_REG	 TC_CV;		/* Counter Value */	AT91_REG	 TC_RA;		/* Register A */	AT91_REG	 TC_RB;		/* Register B */	AT91_REG	 TC_RC;		/* Register C */	AT91_REG	 TC_SR;		/* Status Register */	AT91_REG	 TC_IER;	/* Interrupt Enable Register */	AT91_REG	 TC_IDR;	/* Interrupt Disable Register */	AT91_REG	 TC_IMR;	/* Interrupt Mask Register */} AT91S_TC, *AT91PS_TC;#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 <<  0) /* (TC) MCK/8 */#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 <<  0) /* (TC) MCK/32 */#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 <<  0) /* (TC) MCK/128 */#define AT91C_TC_SLOW_CLOCK	  ((unsigned int) 0x4 <<  0) /* (TC) SLOW CLK*/#define AT91C_TC_XC0_CLOCK	  ((unsigned int) 0x5 <<  0) /* (TC) XC0 */#define AT91C_TC_XC1_CLOCK	  ((unsigned int) 0x6 <<  0) /* (TC) XC1 */#define AT91C_TC_XC2_CLOCK	  ((unsigned int) 0x7 <<  0) /* (TC) XC2 */#define AT91C_TCB_TC0XC0S_NONE	  ((unsigned int) 0x1)       /* (TCB) None signal connected to XC0 */#define AT91C_TCB_TC1XC1S_NONE	  ((unsigned int) 0x1 <<  2) /* (TCB) None signal connected to XC1 */#define AT91C_TCB_TC2XC2S_NONE	  ((unsigned int) 0x1 <<  4) /* (TCB) None signal connected to XC2 */#define AT91C_TC_CLKDIS		  ((unsigned int) 0x1 <<  1) /* (TC) Counter Clock Disable Command */#define AT91C_TC_SWTRG		  ((unsigned int) 0x1 <<  2) /* (TC) Software Trigger Command */#define AT91C_TC_CLKEN		  ((unsigned int) 0x1 <<  0) /* (TC) Counter Clock Enable Command *//*****************************************************************************//*                  SOFTWARE API DEFINITION  FOR Usart                       *//*****************************************************************************/typedef struct _AT91S_USART{	AT91_REG	 US_CR;		/* Control Register */	AT91_REG	 US_MR;		/* Mode Register */	AT91_REG	 US_IER;	/* Interrupt Enable Register */	AT91_REG	 US_IDR;	/* Interrupt Disable Register */	AT91_REG	 US_IMR;	/* Interrupt Mask Register */	AT91_REG	 US_CSR;	/* Channel Status Register */	AT91_REG	 US_RHR;	/* Receiver Holding Register */	AT91_REG	 US_THR;	/* Transmitter Holding Register */	AT91_REG	 US_BRGR;	/* Baud Rate Generator Register */	AT91_REG	 US_RTOR;	/* Receiver Time-out Register */	AT91_REG	 US_TTGR;	/* Transmitter Time-guard Register */	AT91_REG	 Reserved0[5];	/*  */	AT91_REG	 US_FIDI;	/* FI_DI_Ratio Register */	AT91_REG	 US_NER;	/* Nb Errors Register */	AT91_REG	 US_XXR;	/* XON_XOFF Register */	AT91_REG	 US_IF;		/* IRDA_FILTER Register */	AT91_REG	 Reserved1[44];	/*  */	AT91_REG	 US_RPR;	/* Receive Pointer Register */	AT91_REG	 US_RCR;	/* Receive Counter Register */	AT91_REG	 US_TPR;	/* Transmit Pointer Register */	AT91_REG	 US_TCR;	/* Transmit Counter Register */	AT91_REG	 US_RNPR;	/* Receive Next Pointer Register */	AT91_REG	 US_RNCR;	/* Receive Next Counter Register */	AT91_REG	 US_TNPR;	/* Transmit Next Pointer Register */	AT91_REG	 US_TNCR;	/* Transmit Next Counter Register */	AT91_REG	 US_PTCR;	/* PDC Transfer Control Register */	AT91_REG	 US_PTSR;	/* PDC Transfer Status Register */} AT91S_USART, *AT91PS_USART;/*****************************************************************************//*          SOFTWARE API DEFINITION  FOR Clock Generator Controler           *//*****************************************************************************/typedef struct _AT91S_CKGR{	AT91_REG	 CKGR_MOR;	/* Main Oscillator Register */	AT91_REG	 CKGR_MCFR;	/* Main Clock  Frequency Register */	AT91_REG	 CKGR_PLLAR;	/* PLL A Register */	AT91_REG	 CKGR_PLLBR;	/* PLL B Register */} AT91S_CKGR, *AT91PS_CKGR;/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */#define AT91C_CKGR_MOSCEN	((unsigned int) 0x1  <<  0)	/* (CKGR) Main Oscillator Enable */#define AT91C_CKGR_OSCTEST	((unsigned int) 0x1  <<  1)	/* (CKGR) Oscillator Test */#define AT91C_CKGR_OSCOUNT	((unsigned int) 0xFF <<  8)	/* (CKGR) Main Oscillator Start-up Time *//* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */#define AT91C_CKGR_MAINF	((unsigned int) 0xFFFF <<  0)	/* (CKGR) Main Clock Frequency */#define AT91C_CKGR_MAINRDY	((unsigned int) 0x1 << 16)	/* (CKGR) Main Clock Ready *//* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */#define AT91C_CKGR_DIVA		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */#define AT91C_CKGR_DIVA_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */#define AT91C_CKGR_DIVA_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */#define AT91C_CKGR_PLLACOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL A Counter */#define AT91C_CKGR_OUTA		((unsigned int) 0x3   << 14)	/* (CKGR) PLL A Output Frequency Range */#define AT91C_CKGR_OUTA_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLA datasheet */#define AT91C_CKGR_OUTA_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLA datasheet */#define AT91C_CKGR_OUTA_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLA datasheet */#define AT91C_CKGR_OUTA_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLA datasheet */#define AT91C_CKGR_MULA		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL A Multiplier */#define AT91C_CKGR_SRCA		((unsigned int) 0x1   << 29)	/* (CKGR) PLL A Source *//* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */#define AT91C_CKGR_DIVB		((unsigned int) 0xFF  <<  0)	/* (CKGR) Divider Selected */#define AT91C_CKGR_DIVB_0	((unsigned int) 0x0)		/* (CKGR) Divider output is 0 */#define AT91C_CKGR_DIVB_BYPASS	((unsigned int) 0x1)		/* (CKGR) Divider is bypassed */#define AT91C_CKGR_PLLBCOUNT	((unsigned int) 0x3F  <<  8)	/* (CKGR) PLL B Counter */#define AT91C_CKGR_OUTB		((unsigned int) 0x3   << 14)	/* (CKGR) PLL B Output Frequency Range */#define AT91C_CKGR_OUTB_0	((unsigned int) 0x0   << 14)	/* (CKGR) Please refer to the PLLB datasheet */#define AT91C_CKGR_OUTB_1	((unsigned int) 0x1   << 14)	/* (CKGR) Please refer to the PLLB datasheet */#define AT91C_CKGR_OUTB_2	((unsigned int) 0x2   << 14)	/* (CKGR) Please refer to the PLLB datasheet */#define AT91C_CKGR_OUTB_3	((unsigned int) 0x3   << 14)	/* (CKGR) Please refer to the PLLB datasheet */#define AT91C_CKGR_MULB		((unsigned int) 0x7FF << 16)	/* (CKGR) PLL B Multiplier */#define AT91C_CKGR_USB_96M	((unsigned int) 0x1   << 28)	/* (CKGR) Divider for USB Ports */#define AT91C_CKGR_USB_PLL	((unsigned int) 0x1   << 29)	/* (CKGR) PLL Use *//*****************************************************************************//*        SOFTWARE API DEFINITION  FOR Parallel Input Output Controler       *//*****************************************************************************/typedef struct _AT91S_PIO{	AT91_REG	 PIO_PER;	/* PIO Enable Register */	AT91_REG	 PIO_PDR;	/* PIO Disable Register */	AT91_REG	 PIO_PSR;	/* PIO Status Register */	AT91_REG	 Reserved0[1];	/*  */	AT91_REG	 PIO_OER;	/* Output Enable Register */	AT91_REG	 PIO_ODR;	/* Output Disable Registerr */	AT91_REG	 PIO_OSR;	/* Output Status Register */	AT91_REG	 Reserved1[1];	/*  */	AT91_REG	 PIO_IFER;	/* Input Filter Enable Register */	AT91_REG	 PIO_IFDR;	/* Input Filter Disable Register */	AT91_REG	 PIO_IFSR;	/* Input Filter Status Register */	AT91_REG	 Reserved2[1];	/*  */	AT91_REG	 PIO_SODR;	/* Set Output Data Register */	AT91_REG	 PIO_CODR;	/* Clear Output Data Register */	AT91_REG	 PIO_ODSR;	/* Output Data Status Register */	AT91_REG	 PIO_PDSR;	/* Pin Data Status Register */	AT91_REG	 PIO_IER;	/* Interrupt Enable Register */	AT91_REG	 PIO_IDR;	/* Interrupt Disable Register */	AT91_REG	 PIO_IMR;	/* Interrupt Mask Register */	AT91_REG	 PIO_ISR;	/* Interrupt Status Register */	AT91_REG	 PIO_MDER;	/* Multi-driver Enable Register */	AT91_REG	 PIO_MDDR;	/* Multi-driver Disable Register */	AT91_REG	 PIO_MDSR;	/* Multi-driver Status Register */	AT91_REG	 Reserved3[1];	/*  */	AT91_REG	 PIO_PPUDR;	/* Pull-up Disable Register */	AT91_REG	 PIO_PPUER;	/* Pull-up Enable Register */	AT91_REG	 PIO_PPUSR;	/* Pad Pull-up Status Register */	AT91_REG	 Reserved4[1];	/*  */	AT91_REG	 PIO_ASR;	/* Select A Register */	AT91_REG	 PIO_BSR;	/* Select B Register */	AT91_REG	 PIO_ABSR;	/* AB Select Status Register */	AT91_REG	 Reserved5[9];	/*  */	AT91_REG	 PIO_OWER;	/* Output Write Enable Register */	AT91_REG	 PIO_OWDR;	/* Output Write Disable Register */	AT91_REG	 PIO_OWSR;	/* Output Write Status Register */} AT91S_PIO, *AT91PS_PIO;/*****************************************************************************//*              SOFTWARE API DEFINITION  FOR Debug Unit                      *//*****************************************************************************/typedef struct _AT91S_DBGU{	AT91_REG	 DBGU_CR;	/* Control Register */	AT91_REG	 DBGU_MR;	/* Mode Register */	AT91_REG	 DBGU_IER;	/* Interrupt Enable Register */	AT91_REG	 DBGU_IDR;	/* Interrupt Disable Register */	AT91_REG	 DBGU_IMR;	/* Interrupt Mask Register */	AT91_REG	 DBGU_CSR;	/* Channel Status Register */	AT91_REG	 DBGU_RHR;	/* Receiver Holding Register */	AT91_REG	 DBGU_THR;	/* Transmitter Holding Register */	AT91_REG	 DBGU_BRGR;	/* Baud Rate Generator Register */	AT91_REG	 Reserved0[7];	/*  */	AT91_REG	 DBGU_C1R;	/* Chip ID1 Register */	AT91_REG	 DBGU_C2R;	/* Chip ID2 Register */