?? adsp-edn-bf549-extended_def.h
字號(hào):
#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */#define DMA12_NEXT_DESC_PTR 0xFFC01C00 /* DMA Channel 12 Next Descriptor Pointer Register */#define DMA12_START_ADDR 0xFFC01C04 /* DMA Channel 12 Start Address Register */#define DMA12_CONFIG 0xFFC01C08 /* DMA Channel 12 Configuration Register */#define DMA12_X_COUNT 0xFFC01C10 /* DMA Channel 12 X Count Register */#define DMA12_X_MODIFY 0xFFC01C14 /* DMA Channel 12 X Modify Register */#define DMA12_Y_COUNT 0xFFC01C18 /* DMA Channel 12 Y Count Register */#define DMA12_Y_MODIFY 0xFFC01C1C /* DMA Channel 12 Y Modify Register */#define DMA12_CURR_DESC_PTR 0xFFC01C20 /* DMA Channel 12 Current Descriptor Pointer Register */#define DMA12_CURR_ADDR 0xFFC01C24 /* DMA Channel 12 Current Address Register */#define DMA12_IRQ_STATUS 0xFFC01C28 /* DMA Channel 12 Interrupt/Status Register */#define DMA12_PERIPHERAL_MAP 0xFFC01C2C /* DMA Channel 12 Peripheral Map Register */#define DMA12_CURR_X_COUNT 0xFFC01C30 /* DMA Channel 12 Current X Count Register */#define DMA12_CURR_Y_COUNT 0xFFC01C38 /* DMA Channel 12 Current Y Count Register */#define DMA13_NEXT_DESC_PTR 0xFFC01C40 /* DMA Channel 13 Next Descriptor Pointer Register */#define DMA13_START_ADDR 0xFFC01C44 /* DMA Channel 13 Start Address Register */#define DMA13_CONFIG 0xFFC01C48 /* DMA Channel 13 Configuration Register */#define DMA13_X_COUNT 0xFFC01C50 /* DMA Channel 13 X Count Register */#define DMA13_X_MODIFY 0xFFC01C54 /* DMA Channel 13 X Modify Register */#define DMA13_Y_COUNT 0xFFC01C58 /* DMA Channel 13 Y Count Register */#define DMA13_Y_MODIFY 0xFFC01C5C /* DMA Channel 13 Y Modify Register */#define DMA13_CURR_DESC_PTR 0xFFC01C60 /* DMA Channel 13 Current Descriptor Pointer Register */#define DMA13_CURR_ADDR 0xFFC01C64 /* DMA Channel 13 Current Address Register */#define DMA13_IRQ_STATUS 0xFFC01C68 /* DMA Channel 13 Interrupt/Status Register */#define DMA13_PERIPHERAL_MAP 0xFFC01C6C /* DMA Channel 13 Peripheral Map Register */#define DMA13_CURR_X_COUNT 0xFFC01C70 /* DMA Channel 13 Current X Count Register */#define DMA13_CURR_Y_COUNT 0xFFC01C78 /* DMA Channel 13 Current Y Count Register */#define DMA14_NEXT_DESC_PTR 0xFFC01C80 /* DMA Channel 14 Next Descriptor Pointer Register */#define DMA14_START_ADDR 0xFFC01C84 /* DMA Channel 14 Start Address Register */#define DMA14_CONFIG 0xFFC01C88 /* DMA Channel 14 Configuration Register */#define DMA14_X_COUNT 0xFFC01C90 /* DMA Channel 14 X Count Register */#define DMA14_X_MODIFY 0xFFC01C94 /* DMA Channel 14 X Modify Register */#define DMA14_Y_COUNT 0xFFC01C98 /* DMA Channel 14 Y Count Register */#define DMA14_Y_MODIFY 0xFFC01C9C /* DMA Channel 14 Y Modify Register */#define DMA14_CURR_DESC_PTR 0xFFC01CA0 /* DMA Channel 14 Current Descriptor Pointer Register */#define DMA14_CURR_ADDR 0xFFC01CA4 /* DMA Channel 14 Current Address Register */#define DMA14_IRQ_STATUS 0xFFC01CA8 /* DMA Channel 14 Interrupt/Status Register */#define DMA14_PERIPHERAL_MAP 0xFFC01CAC /* DMA Channel 14 Peripheral Map Register */#define DMA14_CURR_X_COUNT 0xFFC01CB0 /* DMA Channel 14 Current X Count Register */#define DMA14_CURR_Y_COUNT 0xFFC01CB8 /* DMA Channel 14 Current Y Count Register */#define DMA15_NEXT_DESC_PTR 0xFFC01CC0 /* DMA Channel 15 Next Descriptor Pointer Register */#define DMA15_START_ADDR 0xFFC01CC4 /* DMA Channel 15 Start Address Register */#define DMA15_CONFIG 0xFFC01CC8 /* DMA Channel 15 Configuration Register */#define DMA15_X_COUNT 0xFFC01CD0 /* DMA Channel 15 X Count Register */#define DMA15_X_MODIFY 0xFFC01CD4 /* DMA Channel 15 X Modify Register */#define DMA15_Y_COUNT 0xFFC01CD8 /* DMA Channel 15 Y Count Register */#define DMA15_Y_MODIFY 0xFFC01CDC /* DMA Channel 15 Y Modify Register */#define DMA15_CURR_DESC_PTR 0xFFC01CE0 /* DMA Channel 15 Current Descriptor Pointer Register */#define DMA15_CURR_ADDR 0xFFC01CE4 /* DMA Channel 15 Current Address Register */#define DMA15_IRQ_STATUS 0xFFC01CE8 /* DMA Channel 15 Interrupt/Status Register */#define DMA15_PERIPHERAL_MAP 0xFFC01CEC /* DMA Channel 15 Peripheral Map Register */#define DMA15_CURR_X_COUNT 0xFFC01CF0 /* DMA Channel 15 Current X Count Register */#define DMA15_CURR_Y_COUNT 0xFFC01CF8 /* DMA Channel 15 Current Y Count Register */#define DMA16_NEXT_DESC_PTR 0xFFC01D00 /* DMA Channel 16 Next Descriptor Pointer Register */#define DMA16_START_ADDR 0xFFC01D04 /* DMA Channel 16 Start Address Register */#define DMA16_CONFIG 0xFFC01D08 /* DMA Channel 16 Configuration Register */#define DMA16_X_COUNT 0xFFC01D10 /* DMA Channel 16 X Count Register */#define DMA16_X_MODIFY 0xFFC01D14 /* DMA Channel 16 X Modify Register */#define DMA16_Y_COUNT 0xFFC01D18 /* DMA Channel 16 Y Count Register */#define DMA16_Y_MODIFY 0xFFC01D1C /* DMA Channel 16 Y Modify Register */#define DMA16_CURR_DESC_PTR 0xFFC01D20 /* DMA Channel 16 Current Descriptor Pointer Register */#define DMA16_CURR_ADDR 0xFFC01D24 /* DMA Channel 16 Current Address Register */#define DMA16_IRQ_STATUS 0xFFC01D28 /* DMA Channel 16 Interrupt/Status Register */#define DMA16_PERIPHERAL_MAP 0xFFC01D2C /* DMA Channel 16 Peripheral Map Register */#define DMA16_CURR_X_COUNT 0xFFC01D30 /* DMA Channel 16 Current X Count Register */#define DMA16_CURR_Y_COUNT 0xFFC01D38 /* DMA Channel 16 Current Y Count Register */#define DMA17_NEXT_DESC_PTR 0xFFC01D40 /* DMA Channel 17 Next Descriptor Pointer Register */#define DMA17_START_ADDR 0xFFC01D44 /* DMA Channel 17 Start Address Register */#define DMA17_CONFIG 0xFFC01D48 /* DMA Channel 17 Configuration Register */#define DMA17_X_COUNT 0xFFC01D50 /* DMA Channel 17 X Count Register */#define DMA17_X_MODIFY 0xFFC01D54 /* DMA Channel 17 X Modify Register */#define DMA17_Y_COUNT 0xFFC01D58 /* DMA Channel 17 Y Count Register */#define DMA17_Y_MODIFY 0xFFC01D5C /* DMA Channel 17 Y Modify Register */#define DMA17_CURR_DESC_PTR 0xFFC01D60 /* DMA Channel 17 Current Descriptor Pointer Register */#define DMA17_CURR_ADDR 0xFFC01D64 /* DMA Channel 17 Current Address Register */#define DMA17_IRQ_STATUS 0xFFC01D68 /* DMA Channel 17 Interrupt/Status Register */#define DMA17_PERIPHERAL_MAP 0xFFC01D6C /* DMA Channel 17 Peripheral Map Register */#define DMA17_CURR_X_COUNT 0xFFC01D70 /* DMA Channel 17 Current X Count Register */#define DMA17_CURR_Y_COUNT 0xFFC01D78 /* DMA Channel 17 Current Y Count Register */#define DMA18_NEXT_DESC_PTR 0xFFC01D80 /* DMA Channel 18 Next Descriptor Pointer Register */#define DMA18_START_ADDR 0xFFC01D84 /* DMA Channel 18 Start Address Register */#define DMA18_CONFIG 0xFFC01D88 /* DMA Channel 18 Configuration Register */#define DMA18_X_COUNT 0xFFC01D90 /* DMA Channel 18 X Count Register */#define DMA18_X_MODIFY 0xFFC01D94 /* DMA Channel 18 X Modify Register */#define DMA18_Y_COUNT 0xFFC01D98 /* DMA Channel 18 Y Count Register */#define DMA18_Y_MODIFY 0xFFC01D9C /* DMA Channel 18 Y Modify Register */#define DMA18_CURR_DESC_PTR 0xFFC01DA0 /* DMA Channel 18 Current Descriptor Pointer Register */#define DMA18_CURR_ADDR 0xFFC01DA4 /* DMA Channel 18 Current Address Register */#define DMA18_IRQ_STATUS 0xFFC01DA8 /* DMA Channel 18 Interrupt/Status Register */#define DMA18_PERIPHERAL_MAP 0xFFC01DAC /* DMA Channel 18 Peripheral Map Register */#define DMA18_CURR_X_COUNT 0xFFC01DB0 /* DMA Channel 18 Current X Count Register */?? 快捷鍵說(shuō)明
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