#define DMA18_CURR_Y_COUNT             0xFFC01DB8 /* DMA Channel 18 Current Y Count Register */#define DMA19_NEXT_DESC_PTR            0xFFC01DC0 /* DMA Channel 19 Next Descriptor Pointer Register */#define DMA19_START_ADDR               0xFFC01DC4 /* DMA Channel 19 Start Address Register */#define DMA19_CONFIG                   0xFFC01DC8 /* DMA Channel 19 Configuration Register */#define DMA19_X_COUNT                  0xFFC01DD0 /* DMA Channel 19 X Count Register */#define DMA19_X_MODIFY                 0xFFC01DD4 /* DMA Channel 19 X Modify Register */#define DMA19_Y_COUNT                  0xFFC01DD8 /* DMA Channel 19 Y Count Register */#define DMA19_Y_MODIFY                 0xFFC01DDC /* DMA Channel 19 Y Modify Register */#define DMA19_CURR_DESC_PTR            0xFFC01DE0 /* DMA Channel 19 Current Descriptor Pointer Register */#define DMA19_CURR_ADDR                0xFFC01DE4 /* DMA Channel 19 Current Address Register */#define DMA19_IRQ_STATUS               0xFFC01DE8 /* DMA Channel 19 Interrupt/Status Register */#define DMA19_PERIPHERAL_MAP           0xFFC01DEC /* DMA Channel 19 Peripheral Map Register */#define DMA19_CURR_X_COUNT             0xFFC01DF0 /* DMA Channel 19 Current X Count Register */#define DMA19_CURR_Y_COUNT             0xFFC01DF8 /* DMA Channel 19 Current Y Count Register */#define DMA20_NEXT_DESC_PTR            0xFFC01E00 /* DMA Channel 20 Next Descriptor Pointer Register */#define DMA20_START_ADDR               0xFFC01E04 /* DMA Channel 20 Start Address Register */#define DMA20_CONFIG                   0xFFC01E08 /* DMA Channel 20 Configuration Register */#define DMA20_X_COUNT                  0xFFC01E10 /* DMA Channel 20 X Count Register */#define DMA20_X_MODIFY                 0xFFC01E14 /* DMA Channel 20 X Modify Register */#define DMA20_Y_COUNT                  0xFFC01E18 /* DMA Channel 20 Y Count Register */#define DMA20_Y_MODIFY                 0xFFC01E1C /* DMA Channel 20 Y Modify Register */#define DMA20_CURR_DESC_PTR            0xFFC01E20 /* DMA Channel 20 Current Descriptor Pointer Register */#define DMA20_CURR_ADDR                0xFFC01E24 /* DMA Channel 20 Current Address Register */#define DMA20_IRQ_STATUS               0xFFC01E28 /* DMA Channel 20 Interrupt/Status Register */#define DMA20_PERIPHERAL_MAP           0xFFC01E2C /* DMA Channel 20 Peripheral Map Register */#define DMA20_CURR_X_COUNT             0xFFC01E30 /* DMA Channel 20 Current X Count Register */#define DMA20_CURR_Y_COUNT             0xFFC01E38 /* DMA Channel 20 Current Y Count Register */#define DMA21_NEXT_DESC_PTR            0xFFC01E40 /* DMA Channel 21 Next Descriptor Pointer Register */#define DMA21_START_ADDR               0xFFC01E44 /* DMA Channel 21 Start Address Register */#define DMA21_CONFIG                   0xFFC01E48 /* DMA Channel 21 Configuration Register */#define DMA21_X_COUNT                  0xFFC01E50 /* DMA Channel 21 X Count Register */#define DMA21_X_MODIFY                 0xFFC01E54 /* DMA Channel 21 X Modify Register */#define DMA21_Y_COUNT                  0xFFC01E58 /* DMA Channel 21 Y Count Register */#define DMA21_Y_MODIFY                 0xFFC01E5C /* DMA Channel 21 Y Modify Register */#define DMA21_CURR_DESC_PTR            0xFFC01E60 /* DMA Channel 21 Current Descriptor Pointer Register */#define DMA21_CURR_ADDR                0xFFC01E64 /* DMA Channel 21 Current Address Register */#define DMA21_IRQ_STATUS               0xFFC01E68 /* DMA Channel 21 Interrupt/Status Register */#define DMA21_PERIPHERAL_MAP           0xFFC01E6C /* DMA Channel 21 Peripheral Map Register */#define DMA21_CURR_X_COUNT             0xFFC01E70 /* DMA Channel 21 Current X Count Register */#define DMA21_CURR_Y_COUNT             0xFFC01E78 /* DMA Channel 21 Current Y Count Register */#define DMA22_NEXT_DESC_PTR            0xFFC01E80 /* DMA Channel 22 Next Descriptor Pointer Register */#define DMA22_START_ADDR               0xFFC01E84 /* DMA Channel 22 Start Address Register */#define DMA22_CONFIG                   0xFFC01E88 /* DMA Channel 22 Configuration Register */#define DMA22_X_COUNT                  0xFFC01E90 /* DMA Channel 22 X Count Register */#define DMA22_X_MODIFY                 0xFFC01E94 /* DMA Channel 22 X Modify Register */#define DMA22_Y_COUNT                  0xFFC01E98 /* DMA Channel 22 Y Count Register */#define DMA22_Y_MODIFY                 0xFFC01E9C /* DMA Channel 22 Y Modify Register */#define DMA22_CURR_DESC_PTR            0xFFC01EA0 /* DMA Channel 22 Current Descriptor Pointer Register */#define DMA22_CURR_ADDR                0xFFC01EA4 /* DMA Channel 22 Current Address Register */#define DMA22_IRQ_STATUS               0xFFC01EA8 /* DMA Channel 22 Interrupt/Status Register */#define DMA22_PERIPHERAL_MAP           0xFFC01EAC /* DMA Channel 22 Peripheral Map Register */#define DMA22_CURR_X_COUNT             0xFFC01EB0 /* DMA Channel 22 Current X Count Register */#define DMA22_CURR_Y_COUNT             0xFFC01EB8 /* DMA Channel 22 Current Y Count Register */#define DMA23_NEXT_DESC_PTR            0xFFC01EC0 /* DMA Channel 23 Next Descriptor Pointer Register */#define DMA23_START_ADDR               0xFFC01EC4 /* DMA Channel 23 Start Address Register */#define DMA23_CONFIG                   0xFFC01EC8 /* DMA Channel 23 Configuration Register */#define DMA23_X_COUNT                  0xFFC01ED0 /* DMA Channel 23 X Count Register */#define DMA23_X_MODIFY                 0xFFC01ED4 /* DMA Channel 23 X Modify Register */#define DMA23_Y_COUNT                  0xFFC01ED8 /* DMA Channel 23 Y Count Register */#define DMA23_Y_MODIFY                 0xFFC01EDC /* DMA Channel 23 Y Modify Register */#define DMA23_CURR_DESC_PTR            0xFFC01EE0 /* DMA Channel 23 Current Descriptor Pointer Register */#define DMA23_CURR_ADDR                0xFFC01EE4 /* DMA Channel 23 Current Address Register */#define DMA23_IRQ_STATUS               0xFFC01EE8 /* DMA Channel 23 Interrupt/Status Register */#define DMA23_PERIPHERAL_MAP           0xFFC01EEC /* DMA Channel 23 Peripheral Map Register */#define DMA23_CURR_X_COUNT             0xFFC01EF0 /* DMA Channel 23 Current X Count Register */#define DMA23_CURR_Y_COUNT             0xFFC01EF8 /* DMA Channel 23 Current Y Count Register */#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */#define MDMA_D0_START_ADDR             0xFFC00F04 /* Memory DMA Stream 0 Destination Start Address Register */#define MDMA_D0_CONFIG                 0xFFC00F08 /* Memory DMA Stream 0 Destination Configuration Register */#define MDMA_D0_X_COUNT                0xFFC00F10 /* Memory DMA Stream 0 Destination X Count Register */#define MDMA_D0_X_MODIFY               0xFFC00F14 /* Memory DMA Stream 0 Destination X Modify Register */#define MDMA_D0_Y_COUNT                0xFFC00F18 /* Memory DMA Stream 0 Destination Y Count Register */#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* Memory DMA Stream 0 Destination Y Modify Register */#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* Memory DMA Stream 0 Destination Current Address Register */#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* Memory DMA Stream 0 Destination Peripheral Map Register */#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* Memory DMA Stream 0 Destination Current X Count Register */#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* Memory DMA Stream 0 Destination Current Y Count Register */#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */#define MDMA_S0_START_ADDR             0xFFC00F44 /* Memory DMA Stream 0 Source Start Address Register */#define MDMA_S0_CONFIG                 0xFFC00F48 /* Memory DMA Stream 0 Source Configuration Register */#define MDMA_S0_X_COUNT                0xFFC00F50 /* Memory DMA Stream 0 Source X Count Register */#define MDMA_S0_X_MODIFY               0xFFC00F54 /* Memory DMA Stream 0 Source X Modify Register */#define MDMA_S0_Y_COUNT                0xFFC00F58 /* Memory DMA Stream 0 Source Y Count Register */#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* Memory DMA Stream 0 Source Y Modify Register */#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* Memory DMA Stream 0 Source Current Address Register */#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* Memory DMA Stream 0 Source Interrupt/Status Register */#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* Memory DMA Stream 0 Source Peripheral Map Register */#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* Memory DMA Stream 0 Source Current X Count Register */#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* Memory DMA Stream 0 Source Current Y Count Register */#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */#define MDMA_D1_START_ADDR             0xFFC00F84 /* Memory DMA Stream 1 Destination Start Address Register */#define MDMA_D1_CONFIG                 0xFFC00F88 /* Memory DMA Stream 1 Destination Configuration Register */#define MDMA_D1_X_COUNT                0xFFC00F90 /* Memory DMA Stream 1 Destination X Count Register */#define MDMA_D1_X_MODIFY               0xFFC00F94 /* Memory DMA Stream 1 Destination X Modify Register */#define MDMA_D1_Y_COUNT                0xFFC00F98 /* Memory DMA Stream 1 Destination Y Count Register */#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* Memory DMA Stream 1 Destination Y Modify Register */#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* Memory DMA Stream 1 Destination Current Address Register */#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* Memory DMA Stream 1 Destination Peripheral Map Register */#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* Memory DMA Stream 1 Destination Current X Count Register */#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* Memory DMA Stream 1 Destination Current Y Count Register */#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */#define MDMA_S1_START_ADDR             0xFFC00FC4 /* Memory DMA Stream 1 Source Start Address Register */#define MDMA_S1_CONFIG                 0xFFC00FC8 /* Memory DMA Stream 1 Source Configuration Register */#define MDMA_S1_X_COUNT                0xFFC00FD0 /* Memory DMA Stream 1 Source X Count Register */#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* Memory DMA Stream 1 Source X Modify Register */#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* Memory DMA Stream 1 Source Y Count Register */#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* Memory DMA Stream 1 Source Y Modify Register */#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* Memory DMA Stream 1 Source Current Address Register */#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* Memory DMA Stream 1 Source Interrupt/Status Register */#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* Memory DMA Stream 1 Source Peripheral Map Register */#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* Memory DMA Stream 1 Source Current X Count Register */#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* Memory DMA Stream 1 Source Current Y Count Register */#define MDMA_D2_NEXT_DESC_PTR          0xFFC01F00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */#define MDMA_D2_START_ADDR             0xFFC01F04 /* Memory DMA Stream 2 Destination Start Address Register */#define MDMA_D2_CONFIG                 0xFFC01F08 /* Memory DMA Stream 2 Destination Configuration Register */#define MDMA_D2_X_COUNT                0xFFC01F10 /* Memory DMA Stream 2 Destination X Count Register */#define MDMA_D2_X_MODIFY               0xFFC01F14 /* Memory DMA Stream 2 Destination X Modify Register */#define MDMA_D2_Y_COUNT                0xFFC01F18 /* Memory DMA Stream 2 Destination Y Count Register */#define MDMA_D2_Y_MODIFY               0xFFC01F1C /* Memory DMA Stream 2 Destination Y Modify Register */#define MDMA_D2_CURR_DESC_PTR          0xFFC01F20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */#define MDMA_D2_CURR_ADDR              0xFFC01F24 /* Memory DMA Stream 2 Destination Current Address Register */#define MDMA_D2_IRQ_STATUS             0xFFC01F28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */#define MDMA_D2_PERIPHERAL_MAP         0xFFC01F2C /* Memory DMA Stream 2 Destination Peripheral Map Register */#define MDMA_D2_CURR_X_COUNT           0xFFC01F30 /* Memory DMA Stream 2 Destination Current X Count Register */#define MDMA_D2_CURR_Y_COUNT           0xFFC01F38 /* Memory DMA Stream 2 Destination Current Y Count Register */#define MDMA_S2_NEXT_DESC_PTR          0xFFC01F40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */#define MDMA_S2_START_ADDR             0xFFC01F44 /* Memory DMA Stream 2 Source Start Address Register */#define MDMA_S2_CONFIG                 0xFFC01F48 /* Memory DMA Stream 2 Source Configuration Register */#define MDMA_S2_X_COUNT                0xFFC01F50 /* Memory DMA Stream 2 Source X Count Register */#define MDMA_S2_X_MODIFY               0xFFC01F54 /* Memory DMA Stream 2 Source X Modify Register */#define MDMA_S2_Y_COUNT                0xFFC01F58 /* Memory DMA Stream 2 Source Y Count Register */#define MDMA_S2_Y_MODIFY               0xFFC01F5C /* Memory DMA Stream 2 Source Y Modify Register */#define MDMA_S2_CURR_DESC_PTR          0xFFC01F60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */#define MDMA_S2_CURR_ADDR              0xFFC01F64 /* Memory DMA Stream 2 Source Current Address Register */