#define MDMA_S2_IRQ_STATUS             0xFFC01F68 /* Memory DMA Stream 2 Source Interrupt/Status Register */#define MDMA_S2_PERIPHERAL_MAP         0xFFC01F6C /* Memory DMA Stream 2 Source Peripheral Map Register */#define MDMA_S2_CURR_X_COUNT           0xFFC01F70 /* Memory DMA Stream 2 Source Current X Count Register */#define MDMA_S2_CURR_Y_COUNT           0xFFC01F78 /* Memory DMA Stream 2 Source Current Y Count Register */#define MDMA_D3_NEXT_DESC_PTR          0xFFC01F80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */#define MDMA_D3_START_ADDR             0xFFC01F84 /* Memory DMA Stream 3 Destination Start Address Register */#define MDMA_D3_CONFIG                 0xFFC01F88 /* Memory DMA Stream 3 Destination Configuration Register */#define MDMA_D3_X_COUNT                0xFFC01F90 /* Memory DMA Stream 3 Destination X Count Register */#define MDMA_D3_X_MODIFY               0xFFC01F94 /* Memory DMA Stream 3 Destination X Modify Register */#define MDMA_D3_Y_COUNT                0xFFC01F98 /* Memory DMA Stream 3 Destination Y Count Register */#define MDMA_D3_Y_MODIFY               0xFFC01F9C /* Memory DMA Stream 3 Destination Y Modify Register */#define MDMA_D3_CURR_DESC_PTR          0xFFC01FA0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */#define MDMA_D3_CURR_ADDR              0xFFC01FA4 /* Memory DMA Stream 3 Destination Current Address Register */#define MDMA_D3_IRQ_STATUS             0xFFC01FA8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */#define MDMA_D3_PERIPHERAL_MAP         0xFFC01FAC /* Memory DMA Stream 3 Destination Peripheral Map Register */#define MDMA_D3_CURR_X_COUNT           0xFFC01FB0 /* Memory DMA Stream 3 Destination Current X Count Register */#define MDMA_D3_CURR_Y_COUNT           0xFFC01FB8 /* Memory DMA Stream 3 Destination Current Y Count Register */#define MDMA_S3_NEXT_DESC_PTR          0xFFC01FC0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */#define MDMA_S3_START_ADDR             0xFFC01FC4 /* Memory DMA Stream 3 Source Start Address Register */#define MDMA_S3_CONFIG                 0xFFC01FC8 /* Memory DMA Stream 3 Source Configuration Register */#define MDMA_S3_X_COUNT                0xFFC01FD0 /* Memory DMA Stream 3 Source X Count Register */#define MDMA_S3_X_MODIFY               0xFFC01FD4 /* Memory DMA Stream 3 Source X Modify Register */#define MDMA_S3_Y_COUNT                0xFFC01FD8 /* Memory DMA Stream 3 Source Y Count Register */#define MDMA_S3_Y_MODIFY               0xFFC01FDC /* Memory DMA Stream 3 Source Y Modify Register */#define MDMA_S3_CURR_DESC_PTR          0xFFC01FE0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */#define MDMA_S3_CURR_ADDR              0xFFC01FE4 /* Memory DMA Stream 3 Source Current Address Register */#define MDMA_S3_IRQ_STATUS             0xFFC01FE8 /* Memory DMA Stream 3 Source Interrupt/Status Register */#define MDMA_S3_PERIPHERAL_MAP         0xFFC01FEC /* Memory DMA Stream 3 Source Peripheral Map Register */#define MDMA_S3_CURR_X_COUNT           0xFFC01FF0 /* Memory DMA Stream 3 Source Current X Count Register */#define MDMA_S3_CURR_Y_COUNT           0xFFC01FF8 /* Memory DMA Stream 3 Source Current Y Count Register */#define HMDMA0_CONTROL                 0xFFC04500 /* Handshake MDMA0 Control Register */#define HMDMA0_ECINIT                  0xFFC04504 /* Handshake MDMA0 Initial Edge Count Register */#define HMDMA0_BCINIT                  0xFFC04508 /* Handshake MDMA0 Initial Block Count Register */#define HMDMA0_ECOUNT                  0xFFC04514 /* Handshake MDMA0 Current Edge Count Register */#define HMDMA0_BCOUNT                  0xFFC04518 /* Handshake MDMA0 Current Block Count Register */#define HMDMA0_ECURGENT                0xFFC0450C /* Handshake MDMA0 Urgent Edge Count Threshhold Register */#define HMDMA0_ECOVERFLOW              0xFFC04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */#define HMDMA1_CONTROL                 0xFFC04540 /* Handshake MDMA1 Control Register */#define HMDMA1_ECINIT                  0xFFC04544 /* Handshake MDMA1 Initial Edge Count Register */#define HMDMA1_BCINIT                  0xFFC04548 /* Handshake MDMA1 Initial Block Count Register */#define HMDMA1_ECURGENT                0xFFC0454C /* Handshake MDMA1 Urgent Edge Count Threshhold Register */#define HMDMA1_ECOVERFLOW              0xFFC04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */#define HMDMA1_ECOUNT                  0xFFC04554 /* Handshake MDMA1 Current Edge Count Register */#define HMDMA1_BCOUNT                  0xFFC04558 /* Handshake MDMA1 Current Block Count Register */#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register */#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register */#define EBIU_MBSCTL                    0xFFC00A0C /* Asynchronous Memory Bank Select Control Register */#define EBIU_ARBSTAT                   0xFFC00A10 /* Asynchronous Memory Arbiter Status Register */#define EBIU_MODE                      0xFFC00A14 /* Asynchronous Mode Control Register */#define EBIU_FCTL                      0xFFC00A18 /* Asynchronous Memory Flash Control Register */#define EBIU_DDRCTL0                   0xFFC00A20 /* DDR Memory Control 0 Register */#define EBIU_DDRCTL1                   0xFFC00A24 /* DDR Memory Control 1 Register */#define EBIU_DDRCTL2                   0xFFC00A28 /* DDR Memory Control 2 Register */#define EBIU_DDRCTL3                   0xFFC00A2C /* DDR Memory Control 3 Register */#define EBIU_DDRQUE                    0xFFC00A30 /* DDR Queue Configuration Register */#define EBIU_ERRADD                    0xFFC00A34 /* DDR Error Address Register */#define EBIU_ERRMST                    0xFFC00A38 /* DDR Error Master Register */#define EBIU_RSTCTL                    0xFFC00A3C /* DDR Reset Control Register */#define EBIU_DDRBRC0                   0xFFC00A60 /* DDR Bank0 Read Count Register */#define EBIU_DDRBRC1                   0xFFC00A64 /* DDR Bank1 Read Count Register */#define EBIU_DDRBRC2                   0xFFC00A68 /* DDR Bank2 Read Count Register */#define EBIU_DDRBRC3                   0xFFC00A6C /* DDR Bank3 Read Count Register */#define EBIU_DDRBRC4                   0xFFC00A70 /* DDR Bank4 Read Count Register */#define EBIU_DDRBRC5                   0xFFC00A74 /* DDR Bank5 Read Count Register */#define EBIU_DDRBRC6                   0xFFC00A78 /* DDR Bank6 Read Count Register */#define EBIU_DDRBRC7                   0xFFC00A7C /* DDR Bank7 Read Count Register */#define EBIU_DDRBWC0                   0xFFC00A80 /* DDR Bank0 Write Count Register */#define EBIU_DDRBWC1                   0xFFC00A84 /* DDR Bank1 Write Count Register */#define EBIU_DDRBWC2                   0xFFC00A88 /* DDR Bank2 Write Count Register */#define EBIU_DDRBWC3                   0xFFC00A8C /* DDR Bank3 Write Count Register */#define EBIU_DDRBWC4                   0xFFC00A90 /* DDR Bank4 Write Count Register */#define EBIU_DDRBWC5                   0xFFC00A94 /* DDR Bank5 Write Count Register */#define EBIU_DDRBWC6                   0xFFC00A98 /* DDR Bank6 Write Count Register */#define EBIU_DDRBWC7                   0xFFC00A9C /* DDR Bank7 Write Count Register */#define EBIU_DDRACCT                   0xFFC00AA0 /* DDR Activation Count Register */#define EBIU_DDRTACT                   0xFFC00AA8 /* DDR Turn Around Count Register */#define EBIU_DDRARCT                   0xFFC00AAC /* DDR Auto-refresh Count Register */#define EBIU_DDRGC0                    0xFFC00AB0 /* DDR Grant Count 0 Register */#define EBIU_DDRGC1                    0xFFC00AB4 /* DDR Grant Count 1 Register */#define EBIU_DDRGC2                    0xFFC00AB8 /* DDR Grant Count 2 Register */#define EBIU_DDRGC3                    0xFFC00ABC /* DDR Grant Count 3 Register */#define EBIU_DDRMCEN                   0xFFC00AC0 /* DDR Metrics Counter Enable Register */#define EBIU_DDRMCCL                   0xFFC00AC4 /* DDR Metrics Counter Clear Register */#define PIXC_CTL                       0xFFC04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */#define PIXC_PPL                       0xFFC04404 /* Holds the number of pixels per line of the display */#define PIXC_LPF                       0xFFC04408 /* Holds the number of lines per frame of the display */#define PIXC_AHSTART                   0xFFC0440C /* Contains horizontal start pixel information of the overlay data (set A) */#define PIXC_AHEND                     0xFFC04410 /* Contains horizontal end pixel information of the overlay data (set A) */#define PIXC_AVSTART                   0xFFC04414 /* Contains vertical start pixel information of the overlay data (set A) */#define PIXC_AVEND                     0xFFC04418 /* Contains vertical end pixel information of the overlay data (set A) */#define PIXC_ATRANSP                   0xFFC0441C /* Contains the transparency ratio (set A) */#define PIXC_BHSTART                   0xFFC04420 /* Contains horizontal start pixel information of the overlay data (set B) */#define PIXC_BHEND                     0xFFC04424 /* Contains horizontal end pixel information of the overlay data (set B) */#define PIXC_BVSTART                   0xFFC04428 /* Contains vertical start pixel information of the overlay data (set B) */#define PIXC_BVEND                     0xFFC0442C /* Contains vertical end pixel information of the overlay data (set B) */#define PIXC_BTRANSP                   0xFFC04430 /* Contains the transparency ratio (set B) */#define PIXC_INTRSTAT                  0xFFC0443C /* Overlay interrupt configuration/status */#define PIXC_RYCON                     0xFFC04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */#define PIXC_GUCON                     0xFFC04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */#define PIXC_BVCON                     0xFFC04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */#define PIXC_CCBIAS                    0xFFC0444C /* Bias values for the color space conversion matrix */#define PIXC_TC                        0xFFC04450 /* Holds the transparent color value */#define HOST_CONTROL                   0xFFC03A00 /* HOSTDP Control Register */#define HOST_STATUS                    0xFFC03A04 /* HOSTDP Status Register */#define HOST_TIMEOUT                   0xFFC03A08 /* HOSTDP Acknowledge Mode Timeout Register */#define PORTA_FER                      0xFFC014C0 /* Function Enable Register */#define PORTA                          0xFFC014C4 /* GPIO Data Register */#define PORTA_SET                      0xFFC014C8 /* GPIO Data Set Register */#define PORTA_CLEAR                    0xFFC014CC /* GPIO Data Clear Register */#define PORTA_DIR_SET                  0xFFC014D0 /* GPIO Direction Set Register */#define PORTA_DIR_CLEAR                0xFFC014D4 /* GPIO Direction Clear Register */#define PORTA_INEN                     0xFFC014D8 /* GPIO Input Enable Register */#define PORTA_MUX                      0xFFC014DC /* Multiplexer Control Register */#define PORTB_FER                      0xFFC014E0 /* Function Enable Register */#define PORTB                          0xFFC014E4 /* GPIO Data Register */#define PORTB_SET                      0xFFC014E8 /* GPIO Data Set Register */#define PORTB_CLEAR                    0xFFC014EC /* GPIO Data Clear Register */#define PORTB_DIR_SET                  0xFFC014F0 /* GPIO Direction Set Register */#define PORTB_DIR_CLEAR                0xFFC014F4 /* GPIO Direction Clear Register */#define PORTB_INEN                     0xFFC014F8 /* GPIO Input Enable Register */#define PORTB_MUX                      0xFFC014FC /* Multiplexer Control Register */#define PORTC_FER                      0xFFC01500 /* Function Enable Register */#define PORTC                          0xFFC01504 /* GPIO Data Register */#define PORTC_SET                      0xFFC01508 /* GPIO Data Set Register */#define PORTC_CLEAR                    0xFFC0150C /* GPIO Data Clear Register */#define PORTC_DIR_SET                  0xFFC01510 /* GPIO Direction Set Register */#define PORTC_DIR_CLEAR                0xFFC01514 /* GPIO Direction Clear Register */#define PORTC_INEN                     0xFFC01518 /* GPIO Input Enable Register */#define PORTC_MUX                      0xFFC0151C /* Multiplexer Control Register */#define PORTD_FER                      0xFFC01520 /* Function Enable Register */#define PORTD                          0xFFC01524 /* GPIO Data Register */#define PORTD_SET                      0xFFC01528 /* GPIO Data Set Register */#define PORTD_CLEAR                    0xFFC0152C /* GPIO Data Clear Register */#define PORTD_DIR_SET                  0xFFC01530 /* GPIO Direction Set Register */#define PORTD_DIR_CLEAR                0xFFC01534 /* GPIO Direction Clear Register */#define PORTD_INEN                     0xFFC01538 /* GPIO Input Enable Register */#define PORTD_MUX                      0xFFC0153C /* Multiplexer Control Register */#define PORTE_FER                      0xFFC01540 /* Function Enable Register */#define PORTE                          0xFFC01544 /* GPIO Data Register */