#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */