/* DO NOT EDIT THIS FILE * Automatically generated by generate-def-headers.xsl * DO NOT EDIT THIS FILE */#ifndef __BFIN_DEF_ADSP_EDN_BF542_extended__#define __BFIN_DEF_ADSP_EDN_BF542_extended__#define SIC_IMASK0                     0xFFC0010C /* System Interrupt Mask Register 0 */#define SIC_IMASK1                     0xFFC00110 /* System Interrupt Mask Register 1 */#define SIC_IMASK2                     0xFFC00114 /* System Interrupt Mask Register 2 */#define SIC_ISR0                       0xFFC00118 /* System Interrupt Status Register 0 */#define SIC_ISR1                       0xFFC0011C /* System Interrupt Status Register 1 */#define SIC_ISR2                       0xFFC00120 /* System Interrupt Status Register 2 */#define SIC_IWR0                       0xFFC00124 /* System Interrupt Wakeup Register 0 */#define SIC_IWR1                       0xFFC00128 /* System Interrupt Wakeup Register 1 */#define SIC_IWR2                       0xFFC0012C /* System Interrupt Wakeup Register 2 */#define SIC_IAR0                       0xFFC00130 /* System Interrupt Assignment Register 0 */#define SIC_IAR1                       0xFFC00134 /* System Interrupt Assignment Register 1 */#define SIC_IAR2                       0xFFC00138 /* System Interrupt Assignment Register 2 */#define SIC_IAR3                       0xFFC0013C /* System Interrupt Assignment Register 3 */#define SIC_IAR4                       0xFFC00140 /* System Interrupt Assignment Register 4 */#define SIC_IAR5                       0xFFC00144 /* System Interrupt Assignment Register 5 */#define SIC_IAR6                       0xFFC00148 /* System Interrupt Assignment Register 6 */#define SIC_IAR7                       0xFFC0014C /* System Interrupt Assignment Register 7 */#define SIC_IAR8                       0xFFC00150 /* System Interrupt Assignment Register 8 */#define SIC_IAR9                       0xFFC00154 /* System Interrupt Assignment Register 9 */#define SIC_IAR10                      0xFFC00158 /* System Interrupt Assignment Register 10 */#define SIC_IAR11                      0xFFC0015C /* System Interrupt Assignment Register 11 */#define DMAC0_TCPER                    0xFFC00B0C /* DMA Controller 0 Traffic Control Periods Register */#define DMAC0_TCCNT                    0xFFC00B10 /* DMA Controller 0 Current Counts Register */#define DMAC1_TCPER                    0xFFC01B0C /* DMA Controller 1 Traffic Control Periods Register */#define DMAC1_TCCNT                    0xFFC01B10 /* DMA Controller 1 Current Counts Register */#define DMAC1_PERIMUX                  0xFFC04340 /* DMA Controller 1 Peripheral Multiplexer Register */#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */