#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */