/* DO NOT EDIT THIS FILE * Automatically generated by generate-cdef-headers.xsl * DO NOT EDIT THIS FILE */#ifndef __BFIN_CDEF_ADSP_EDN_BF52x_extended__#define __BFIN_CDEF_ADSP_EDN_BF52x_extended__#define pSIC_RVECT                     ((uint32_t volatile *)SIC_RVECT) /* Interrupt Reset Vector Address Register */#define bfin_read_SIC_RVECT()          bfin_read32(SIC_RVECT)#define bfin_write_SIC_RVECT(val)      bfin_write32(SIC_RVECT, val)#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* Interrupt Mask Register */#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* Interrupt Assignment Register 0 */#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* Interrupt Assignment Register 1 */#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* Interrupt Assignment Register 2 */#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* Interrupt Assignment Register 3 */#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* Interrupt Status Register */#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* Interrupt Wakeup Register */#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* Interrupt Mask register of SIC2 */#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* Interrupt Assignment register4 */#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* Interrupt Assignment register5 */#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* Interrupt Assignment register6 */#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* Interrupt Assignment register7 */#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* Interrupt Status register */#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* Interrupt Wakeup register */#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Time Register */#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Holding register */#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer register */#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)#define pUART0_IER                     ((uint16_t volatile *)UART0_IER) /* Interrupt Enable Register */#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)#define pUART0_IIR                     ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification Register */#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* SCR Scratch Register */#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)#define pSPI_CTL                       ((uint16_t volatile *)SPI_CTL) /* SPI Control Register */#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)#define pSPI_FLG                       ((uint16_t volatile *)SPI_FLG) /* SPI Flag register */#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)#define pSPI_STAT                      ((uint16_t volatile *)SPI_STAT) /* SPI Status register */#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)#define pSPI_TDBR                      ((uint16_t volatile *)SPI_TDBR) /* SPI Transmit Data Buffer Register */#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)#define pSPI_RDBR                      ((uint16_t volatile *)SPI_RDBR) /* SPI Receive Data Buffer Register */#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)#define pSPI_BAUD                      ((uint16_t volatile *)SPI_BAUD) /* SPI Baud rate Register */#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)#define pSPI_SHADOW                    ((uint16_t volatile *)SPI_SHADOW) /* SPI_RDBR Shadow Register */#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */