#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS) /* Instruction Cache Programmable Look-Aside Buffer Status */#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)#define pICPLB_FAULT_ADDR              ((void * volatile *)ICPLB_FAULT_ADDR) /* Instruction Cache Programmable Look-Aside Buffer Fault Address */#define bfin_read_ICPLB_FAULT_ADDR()   bfin_readPTR(ICPLB_FAULT_ADDR)#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_writePTR(ICPLB_FAULT_ADDR, val)#define pICPLB_ADDR0                   ((void * volatile *)ICPLB_ADDR0) /* Instruction Cacheability Protection Lookaside Buffer 0 */#define bfin_read_ICPLB_ADDR0()        bfin_readPTR(ICPLB_ADDR0)#define bfin_write_ICPLB_ADDR0(val)    bfin_writePTR(ICPLB_ADDR0, val)#define pICPLB_ADDR1                   ((void * volatile *)ICPLB_ADDR1) /* Instruction Cacheability Protection Lookaside Buffer 1 */#define bfin_read_ICPLB_ADDR1()        bfin_readPTR(ICPLB_ADDR1)#define bfin_write_ICPLB_ADDR1(val)    bfin_writePTR(ICPLB_ADDR1, val)#define pICPLB_ADDR2                   ((void * volatile *)ICPLB_ADDR2) /* Instruction Cacheability Protection Lookaside Buffer 2 */#define bfin_read_ICPLB_ADDR2()        bfin_readPTR(ICPLB_ADDR2)#define bfin_write_ICPLB_ADDR2(val)    bfin_writePTR(ICPLB_ADDR2, val)#define pICPLB_ADDR3                   ((void * volatile *)ICPLB_ADDR3) /* Instruction Cacheability Protection Lookaside Buffer 3 */#define bfin_read_ICPLB_ADDR3()        bfin_readPTR(ICPLB_ADDR3)#define bfin_write_ICPLB_ADDR3(val)    bfin_writePTR(ICPLB_ADDR3, val)#define pICPLB_ADDR4                   ((void * volatile *)ICPLB_ADDR4) /* Instruction Cacheability Protection Lookaside Buffer 4 */#define bfin_read_ICPLB_ADDR4()        bfin_readPTR(ICPLB_ADDR4)#define bfin_write_ICPLB_ADDR4(val)    bfin_writePTR(ICPLB_ADDR4, val)#define pICPLB_ADDR5                   ((void * volatile *)ICPLB_ADDR5) /* Instruction Cacheability Protection Lookaside Buffer 5 */#define bfin_read_ICPLB_ADDR5()        bfin_readPTR(ICPLB_ADDR5)#define bfin_write_ICPLB_ADDR5(val)    bfin_writePTR(ICPLB_ADDR5, val)#define pICPLB_ADDR6                   ((void * volatile *)ICPLB_ADDR6) /* Instruction Cacheability Protection Lookaside Buffer 6 */#define bfin_read_ICPLB_ADDR6()        bfin_readPTR(ICPLB_ADDR6)#define bfin_write_ICPLB_ADDR6(val)    bfin_writePTR(ICPLB_ADDR6, val)#define pICPLB_ADDR7                   ((void * volatile *)ICPLB_ADDR7) /* Instruction Cacheability Protection Lookaside Buffer 7 */#define bfin_read_ICPLB_ADDR7()        bfin_readPTR(ICPLB_ADDR7)#define bfin_write_ICPLB_ADDR7(val)    bfin_writePTR(ICPLB_ADDR7, val)#define pICPLB_ADDR8                   ((void * volatile *)ICPLB_ADDR8) /* Instruction Cacheability Protection Lookaside Buffer 8 */#define bfin_read_ICPLB_ADDR8()        bfin_readPTR(ICPLB_ADDR8)#define bfin_write_ICPLB_ADDR8(val)    bfin_writePTR(ICPLB_ADDR8, val)#define pICPLB_ADDR9                   ((void * volatile *)ICPLB_ADDR9) /* Instruction Cacheability Protection Lookaside Buffer 9 */#define bfin_read_ICPLB_ADDR9()        bfin_readPTR(ICPLB_ADDR9)#define bfin_write_ICPLB_ADDR9(val)    bfin_writePTR(ICPLB_ADDR9, val)#define pICPLB_ADDR10                  ((void * volatile *)ICPLB_ADDR10) /* Instruction Cacheability Protection Lookaside Buffer 10 */#define bfin_read_ICPLB_ADDR10()       bfin_readPTR(ICPLB_ADDR10)#define bfin_write_ICPLB_ADDR10(val)   bfin_writePTR(ICPLB_ADDR10, val)#define pICPLB_ADDR11                  ((void * volatile *)ICPLB_ADDR11) /* Instruction Cacheability Protection Lookaside Buffer 11 */#define bfin_read_ICPLB_ADDR11()       bfin_readPTR(ICPLB_ADDR11)#define bfin_write_ICPLB_ADDR11(val)   bfin_writePTR(ICPLB_ADDR11, val)#define pICPLB_ADDR12                  ((void * volatile *)ICPLB_ADDR12) /* Instruction Cacheability Protection Lookaside Buffer 12 */#define bfin_read_ICPLB_ADDR12()       bfin_readPTR(ICPLB_ADDR12)#define bfin_write_ICPLB_ADDR12(val)   bfin_writePTR(ICPLB_ADDR12, val)#define pICPLB_ADDR13                  ((void * volatile *)ICPLB_ADDR13) /* Instruction Cacheability Protection Lookaside Buffer 13 */#define bfin_read_ICPLB_ADDR13()       bfin_readPTR(ICPLB_ADDR13)#define bfin_write_ICPLB_ADDR13(val)   bfin_writePTR(ICPLB_ADDR13, val)#define pICPLB_ADDR14                  ((void * volatile *)ICPLB_ADDR14) /* Instruction Cacheability Protection Lookaside Buffer 14 */#define bfin_read_ICPLB_ADDR14()       bfin_readPTR(ICPLB_ADDR14)#define bfin_write_ICPLB_ADDR14(val)   bfin_writePTR(ICPLB_ADDR14, val)#define pICPLB_ADDR15                  ((void * volatile *)ICPLB_ADDR15) /* Instruction Cacheability Protection Lookaside Buffer 15 */#define bfin_read_ICPLB_ADDR15()       bfin_readPTR(ICPLB_ADDR15)#define bfin_write_ICPLB_ADDR15(val)   bfin_writePTR(ICPLB_ADDR15, val)#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0) /* Instruction Cache 0 Status */#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1) /* Instruction Cache 1 Status */#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2) /* Instruction Cache 2 Status */#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3) /* Instruction Cache 3 Status */#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4) /* Instruction Cache 4 Status */#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5) /* Instruction Cache 5 Status */#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6) /* Instruction Cache 6 Status */#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7) /* Instruction Cache 7 Status */#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8) /* Instruction Cache 8 Status */#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9) /* Instruction Cache 9 Status */#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10) /* Instruction Cache 10 Status */#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11) /* Instruction Cache 11 Status */#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12) /* Instruction Cache 12 Status */#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13) /* Instruction Cache 13 Status */#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14) /* Instruction Cache 14 Status */#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15) /* Instruction Cache 15 Status */#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND) /* Instruction Test Command Register */#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0) /* Instruction Test Data Register */#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1) /* Instruction Test Data Register */#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)#define pEVT0                          ((void * volatile *)EVT0) /* Event Vector 0 ESR Address */#define bfin_read_EVT0()               bfin_readPTR(EVT0)#define bfin_write_EVT0(val)           bfin_writePTR(EVT0, val)#define pEVT1                          ((void * volatile *)EVT1) /* Event Vector 1 ESR Address */#define bfin_read_EVT1()               bfin_readPTR(EVT1)#define bfin_write_EVT1(val)           bfin_writePTR(EVT1, val)#define pEVT2                          ((void * volatile *)EVT2) /* Event Vector 2 ESR Address */#define bfin_read_EVT2()               bfin_readPTR(EVT2)#define bfin_write_EVT2(val)           bfin_writePTR(EVT2, val)#define pEVT3                          ((void * volatile *)EVT3) /* Event Vector 3 ESR Address */#define bfin_read_EVT3()               bfin_readPTR(EVT3)#define bfin_write_EVT3(val)           bfin_writePTR(EVT3, val)#define pEVT4                          ((void * volatile *)EVT4) /* Event Vector 4 ESR Address */#define bfin_read_EVT4()               bfin_readPTR(EVT4)#define bfin_write_EVT4(val)           bfin_writePTR(EVT4, val)#define pEVT5                          ((void * volatile *)EVT5) /* Event Vector 5 ESR Address */#define bfin_read_EVT5()               bfin_readPTR(EVT5)#define bfin_write_EVT5(val)           bfin_writePTR(EVT5, val)#define pEVT6                          ((void * volatile *)EVT6) /* Event Vector 6 ESR Address */#define bfin_read_EVT6()               bfin_readPTR(EVT6)#define bfin_write_EVT6(val)           bfin_writePTR(EVT6, val)#define pEVT7                          ((void * volatile *)EVT7) /* Event Vector 7 ESR Address */#define bfin_read_EVT7()               bfin_readPTR(EVT7)#define bfin_write_EVT7(val)           bfin_writePTR(EVT7, val)#define pEVT8                          ((void * volatile *)EVT8) /* Event Vector 8 ESR Address */#define bfin_read_EVT8()               bfin_readPTR(EVT8)#define bfin_write_EVT8(val)           bfin_writePTR(EVT8, val)#define pEVT9                          ((void * volatile *)EVT9) /* Event Vector 9 ESR Address */#define bfin_read_EVT9()               bfin_readPTR(EVT9)#define bfin_write_EVT9(val)           bfin_writePTR(EVT9, val)#define pEVT10                         ((void * volatile *)EVT10) /* Event Vector 10 ESR Address */