/* DO NOT EDIT THIS FILE * Automatically generated by generate-cdef-headers.xsl * DO NOT EDIT THIS FILE */#ifndef __BFIN_CDEF_ADSP_BF526_proc__#define __BFIN_CDEF_ADSP_BF526_proc__#include "../mach-common/ADSP-EDN-core_cdef.h"#include "ADSP-EDN-BF52x-extended_cdef.h"#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divide Register */#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)#define pCHIPID                        ((uint32_t volatile *)CHIPID)#define bfin_read_CHIPID()             bfin_read32(CHIPID)#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)#define pSWRST                         ((uint16_t volatile *)SWRST) /* Software Reset Register */#define bfin_read_SWRST()              bfin_read16(SWRST)#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)#define pSYSCR                         ((uint16_t volatile *)SYSCR) /* System Configuration register */#define bfin_read_SYSCR()              bfin_read16(SYSCR)#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)#define pSRAM_BASE_ADDR                ((void * volatile *)SRAM_BASE_ADDR) /* SRAM Base Address (Read Only) */#define bfin_read_SRAM_BASE_ADDR()     bfin_readPTR(SRAM_BASE_ADDR)#define bfin_write_SRAM_BASE_ADDR(val) bfin_writePTR(SRAM_BASE_ADDR, val)#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL) /* Data memory control */#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS) /* Data Cache Programmable Look-Aside Buffer Status */#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR) /* Data Cache Programmable Look-Aside Buffer Fault Address */#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)#define pDCPLB_ADDR0                   ((void * volatile *)DCPLB_ADDR0) /* Data Cache Protection Lookaside Buffer 0 */#define bfin_read_DCPLB_ADDR0()        bfin_readPTR(DCPLB_ADDR0)#define bfin_write_DCPLB_ADDR0(val)    bfin_writePTR(DCPLB_ADDR0, val)#define pDCPLB_ADDR1                   ((void * volatile *)DCPLB_ADDR1) /* Data Cache Protection Lookaside Buffer 1 */#define bfin_read_DCPLB_ADDR1()        bfin_readPTR(DCPLB_ADDR1)#define bfin_write_DCPLB_ADDR1(val)    bfin_writePTR(DCPLB_ADDR1, val)#define pDCPLB_ADDR2                   ((void * volatile *)DCPLB_ADDR2) /* Data Cache Protection Lookaside Buffer 2 */#define bfin_read_DCPLB_ADDR2()        bfin_readPTR(DCPLB_ADDR2)#define bfin_write_DCPLB_ADDR2(val)    bfin_writePTR(DCPLB_ADDR2, val)#define pDCPLB_ADDR3                   ((void * volatile *)DCPLB_ADDR3) /* Data Cache Protection Lookaside Buffer 3 */#define bfin_read_DCPLB_ADDR3()        bfin_readPTR(DCPLB_ADDR3)#define bfin_write_DCPLB_ADDR3(val)    bfin_writePTR(DCPLB_ADDR3, val)#define pDCPLB_ADDR4                   ((void * volatile *)DCPLB_ADDR4) /* Data Cache Protection Lookaside Buffer 4 */#define bfin_read_DCPLB_ADDR4()        bfin_readPTR(DCPLB_ADDR4)#define bfin_write_DCPLB_ADDR4(val)    bfin_writePTR(DCPLB_ADDR4, val)#define pDCPLB_ADDR5                   ((void * volatile *)DCPLB_ADDR5) /* Data Cache Protection Lookaside Buffer 5 */#define bfin_read_DCPLB_ADDR5()        bfin_readPTR(DCPLB_ADDR5)#define bfin_write_DCPLB_ADDR5(val)    bfin_writePTR(DCPLB_ADDR5, val)#define pDCPLB_ADDR6                   ((void * volatile *)DCPLB_ADDR6) /* Data Cache Protection Lookaside Buffer 6 */#define bfin_read_DCPLB_ADDR6()        bfin_readPTR(DCPLB_ADDR6)#define bfin_write_DCPLB_ADDR6(val)    bfin_writePTR(DCPLB_ADDR6, val)#define pDCPLB_ADDR7                   ((void * volatile *)DCPLB_ADDR7) /* Data Cache Protection Lookaside Buffer 7 */#define bfin_read_DCPLB_ADDR7()        bfin_readPTR(DCPLB_ADDR7)#define bfin_write_DCPLB_ADDR7(val)    bfin_writePTR(DCPLB_ADDR7, val)#define pDCPLB_ADDR8                   ((void * volatile *)DCPLB_ADDR8) /* Data Cache Protection Lookaside Buffer 8 */#define bfin_read_DCPLB_ADDR8()        bfin_readPTR(DCPLB_ADDR8)#define bfin_write_DCPLB_ADDR8(val)    bfin_writePTR(DCPLB_ADDR8, val)#define pDCPLB_ADDR9                   ((void * volatile *)DCPLB_ADDR9) /* Data Cache Protection Lookaside Buffer 9 */#define bfin_read_DCPLB_ADDR9()        bfin_readPTR(DCPLB_ADDR9)#define bfin_write_DCPLB_ADDR9(val)    bfin_writePTR(DCPLB_ADDR9, val)#define pDCPLB_ADDR10                  ((void * volatile *)DCPLB_ADDR10) /* Data Cache Protection Lookaside Buffer 10 */#define bfin_read_DCPLB_ADDR10()       bfin_readPTR(DCPLB_ADDR10)#define bfin_write_DCPLB_ADDR10(val)   bfin_writePTR(DCPLB_ADDR10, val)#define pDCPLB_ADDR11                  ((void * volatile *)DCPLB_ADDR11) /* Data Cache Protection Lookaside Buffer 11 */#define bfin_read_DCPLB_ADDR11()       bfin_readPTR(DCPLB_ADDR11)#define bfin_write_DCPLB_ADDR11(val)   bfin_writePTR(DCPLB_ADDR11, val)#define pDCPLB_ADDR12                  ((void * volatile *)DCPLB_ADDR12) /* Data Cache Protection Lookaside Buffer 12 */#define bfin_read_DCPLB_ADDR12()       bfin_readPTR(DCPLB_ADDR12)#define bfin_write_DCPLB_ADDR12(val)   bfin_writePTR(DCPLB_ADDR12, val)#define pDCPLB_ADDR13                  ((void * volatile *)DCPLB_ADDR13) /* Data Cache Protection Lookaside Buffer 13 */#define bfin_read_DCPLB_ADDR13()       bfin_readPTR(DCPLB_ADDR13)#define bfin_write_DCPLB_ADDR13(val)   bfin_writePTR(DCPLB_ADDR13, val)#define pDCPLB_ADDR14                  ((void * volatile *)DCPLB_ADDR14) /* Data Cache Protection Lookaside Buffer 14 */#define bfin_read_DCPLB_ADDR14()       bfin_readPTR(DCPLB_ADDR14)#define bfin_write_DCPLB_ADDR14(val)   bfin_writePTR(DCPLB_ADDR14, val)#define pDCPLB_ADDR15                  ((void * volatile *)DCPLB_ADDR15) /* Data Cache Protection Lookaside Buffer 15 */#define bfin_read_DCPLB_ADDR15()       bfin_readPTR(DCPLB_ADDR15)#define bfin_write_DCPLB_ADDR15(val)   bfin_writePTR(DCPLB_ADDR15, val)#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0) /* Data Cache 0 Status */#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1) /* Data Cache 1 Status */#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2) /* Data Cache 2 Status */#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3) /* Data Cache 3 Status */#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4) /* Data Cache 4 Status */#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5) /* Data Cache 5 Status */#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6) /* Data Cache 6 Status */#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7) /* Data Cache 7 Status */#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8) /* Data Cache 8 Status */#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9) /* Data Cache 9 Status */#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10) /* Data Cache 10 Status */#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11) /* Data Cache 11 Status */#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12) /* Data Cache 12 Status */#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13) /* Data Cache 13 Status */#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14) /* Data Cache 14 Status */#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15) /* Data Cache 15 Status */#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND) /* Data Test Command Register */#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0) /* Data Test Data Register */#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1) /* Data Test Data Register */#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL) /* Instruction Memory Control */#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)