/* DO NOT EDIT THIS FILE * Automatically generated by generate-def-headers.xsl * DO NOT EDIT THIS FILE */#ifndef __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__#define __BFIN_DEF_ADSP_EDN_DUAL_CORE_extended__#define PLL_CTL                        0xFFC00000#define PLL_DIV                        0xFFC00004#define VR_CTL                         0xFFC00008#define PLL_STAT                       0xFFC0000C#define PLL_LOCKCNT                    0xFFC00010#define CHIPID                         0xFFC00014#define SPI_CTL                        0xFFC00500#define SPI_FLG                        0xFFC00504#define SPI_STAT                       0xFFC00508#define SPI_TDBR                       0xFFC0050C#define SPI_RDBR                       0xFFC00510#define SPI_BAUD                       0xFFC00514#define SPI_SHADOW                     0xFFC00518#define WDOGA_CTL                      0xFFC00200#define WDOGA_CNT                      0xFFC00204#define WDOGA_STAT                     0xFFC00208#define WDOGB_CTL                      0xFFC01200#define WDOGB_CNT                      0xFFC01204#define WDOGB_STAT                     0xFFC01208#define DMA1_TC_PER                    0xFFC01B0C /* Traffic Control Periods */#define DMA1_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */#define DMA1_0_CONFIG                  0xFFC01C08#define DMA1_0_NEXT_DESC_PTR           0xFFC01C00#define DMA1_0_START_ADDR              0xFFC01C04#define DMA1_0_X_COUNT                 0xFFC01C10#define DMA1_0_Y_COUNT                 0xFFC01C18#define DMA1_0_X_MODIFY                0xFFC01C14#define DMA1_0_Y_MODIFY                0xFFC01C1C#define DMA1_0_CURR_DESC_PTR           0xFFC01C20#define DMA1_0_CURR_ADDR               0xFFC01C24#define DMA1_0_CURR_X_COUNT            0xFFC01C30#define DMA1_0_CURR_Y_COUNT            0xFFC01C38#define DMA1_0_IRQ_STATUS              0xFFC01C28#define DMA1_0_PERIPHERAL_MAP          0xFFC01C2C#define DMA1_1_CONFIG                  0xFFC01C48#define DMA1_1_NEXT_DESC_PTR           0xFFC01C40#define DMA1_1_START_ADDR              0xFFC01C44#define DMA1_1_X_COUNT                 0xFFC01C50#define DMA1_1_Y_COUNT                 0xFFC01C58#define DMA1_1_X_MODIFY                0xFFC01C54#define DMA1_1_Y_MODIFY                0xFFC01C5C#define DMA1_1_CURR_DESC_PTR           0xFFC01C60#define DMA1_1_CURR_ADDR               0xFFC01C64#define DMA1_1_CURR_X_COUNT            0xFFC01C70#define DMA1_1_CURR_Y_COUNT            0xFFC01C78#define DMA1_1_IRQ_STATUS              0xFFC01C68#define DMA1_1_PERIPHERAL_MAP          0xFFC01C6C#define DMA1_2_CONFIG                  0xFFC01C88#define DMA1_2_NEXT_DESC_PTR           0xFFC01C80#define DMA1_2_START_ADDR              0xFFC01C84#define DMA1_2_X_COUNT                 0xFFC01C90#define DMA1_2_Y_COUNT                 0xFFC01C98#define DMA1_2_X_MODIFY                0xFFC01C94#define DMA1_2_Y_MODIFY                0xFFC01C9C#define DMA1_2_CURR_DESC_PTR           0xFFC01CA0#define DMA1_2_CURR_ADDR               0xFFC01CA4#define DMA1_2_CURR_X_COUNT            0xFFC01CB0#define DMA1_2_CURR_Y_COUNT            0xFFC01CB8#define DMA1_2_IRQ_STATUS              0xFFC01CA8#define DMA1_2_PERIPHERAL_MAP          0xFFC01CAC#define DMA1_3_CONFIG                  0xFFC01CC8#define DMA1_3_NEXT_DESC_PTR           0xFFC01CC0#define DMA1_3_START_ADDR              0xFFC01CC4#define DMA1_3_X_COUNT                 0xFFC01CD0#define DMA1_3_Y_COUNT                 0xFFC01CD8#define DMA1_3_X_MODIFY                0xFFC01CD4#define DMA1_3_Y_MODIFY                0xFFC01CDC#define DMA1_3_CURR_DESC_PTR           0xFFC01CE0#define DMA1_3_CURR_ADDR               0xFFC01CE4#define DMA1_3_CURR_X_COUNT            0xFFC01CF0#define DMA1_3_CURR_Y_COUNT            0xFFC01CF8#define DMA1_3_IRQ_STATUS              0xFFC01CE8#define DMA1_3_PERIPHERAL_MAP          0xFFC01CEC#define DMA1_4_CONFIG                  0xFFC01D08#define DMA1_4_NEXT_DESC_PTR           0xFFC01D00#define DMA1_4_START_ADDR              0xFFC01D04#define DMA1_4_X_COUNT                 0xFFC01D10#define DMA1_4_Y_COUNT                 0xFFC01D18#define DMA1_4_X_MODIFY                0xFFC01D14#define DMA1_4_Y_MODIFY                0xFFC01D1C#define DMA1_4_CURR_DESC_PTR           0xFFC01D20#define DMA1_4_CURR_ADDR               0xFFC01D24#define DMA1_4_CURR_X_COUNT            0xFFC01D30#define DMA1_4_CURR_Y_COUNT            0xFFC01D38#define DMA1_4_IRQ_STATUS              0xFFC01D28#define DMA1_4_PERIPHERAL_MAP          0xFFC01D2C#define DMA1_5_CONFIG                  0xFFC01D48#define DMA1_5_NEXT_DESC_PTR           0xFFC01D40#define DMA1_5_START_ADDR              0xFFC01D44#define DMA1_5_X_COUNT                 0xFFC01D50#define DMA1_5_Y_COUNT                 0xFFC01D58#define DMA1_5_X_MODIFY                0xFFC01D54#define DMA1_5_Y_MODIFY                0xFFC01D5C#define DMA1_5_CURR_DESC_PTR           0xFFC01D60#define DMA1_5_CURR_ADDR               0xFFC01D64#define DMA1_5_CURR_X_COUNT            0xFFC01D70#define DMA1_5_CURR_Y_COUNT            0xFFC01D78#define DMA1_5_IRQ_STATUS              0xFFC01D68#define DMA1_5_PERIPHERAL_MAP          0xFFC01D6C#define DMA1_6_CONFIG                  0xFFC01D88#define DMA1_6_NEXT_DESC_PTR           0xFFC01D80#define DMA1_6_START_ADDR              0xFFC01D84#define DMA1_6_X_COUNT                 0xFFC01D90#define DMA1_6_Y_COUNT                 0xFFC01D98#define DMA1_6_X_MODIFY                0xFFC01D94#define DMA1_6_Y_MODIFY                0xFFC01D9C#define DMA1_6_CURR_DESC_PTR           0xFFC01DA0#define DMA1_6_CURR_ADDR               0xFFC01DA4#define DMA1_6_CURR_X_COUNT            0xFFC01DB0#define DMA1_6_CURR_Y_COUNT            0xFFC01DB8#define DMA1_6_IRQ_STATUS              0xFFC01DA8#define DMA1_6_PERIPHERAL_MAP          0xFFC01DAC#define DMA1_7_CONFIG                  0xFFC01DC8#define DMA1_7_NEXT_DESC_PTR           0xFFC01DC0#define DMA1_7_START_ADDR              0xFFC01DC4#define DMA1_7_X_COUNT                 0xFFC01DD0#define DMA1_7_Y_COUNT                 0xFFC01DD8#define DMA1_7_X_MODIFY                0xFFC01DD4#define DMA1_7_Y_MODIFY                0xFFC01DDC#define DMA1_7_CURR_DESC_PTR           0xFFC01DE0#define DMA1_7_CURR_ADDR               0xFFC01DE4#define DMA1_7_CURR_X_COUNT            0xFFC01DF0#define DMA1_7_CURR_Y_COUNT            0xFFC01DF8#define DMA1_7_IRQ_STATUS              0xFFC01DE8#define DMA1_7_PERIPHERAL_MAP          0xFFC01DEC#define DMA1_8_CONFIG                  0xFFC01E08#define DMA1_8_NEXT_DESC_PTR           0xFFC01E00#define DMA1_8_START_ADDR              0xFFC01E04#define DMA1_8_X_COUNT                 0xFFC01E10#define DMA1_8_Y_COUNT                 0xFFC01E18#define DMA1_8_X_MODIFY                0xFFC01E14#define DMA1_8_Y_MODIFY                0xFFC01E1C#define DMA1_8_CURR_DESC_PTR           0xFFC01E20#define DMA1_8_CURR_ADDR               0xFFC01E24#define DMA1_8_CURR_X_COUNT            0xFFC01E30#define DMA1_8_CURR_Y_COUNT            0xFFC01E38#define DMA1_8_IRQ_STATUS              0xFFC01E28#define DMA1_8_PERIPHERAL_MAP          0xFFC01E2C#define DMA1_9_CONFIG                  0xFFC01E48#define DMA1_9_NEXT_DESC_PTR           0xFFC01E40#define DMA1_9_START_ADDR              0xFFC01E44#define DMA1_9_X_COUNT                 0xFFC01E50#define DMA1_9_Y_COUNT                 0xFFC01E58#define DMA1_9_X_MODIFY                0xFFC01E54#define DMA1_9_Y_MODIFY                0xFFC01E5C#define DMA1_9_CURR_DESC_PTR           0xFFC01E60#define DMA1_9_CURR_ADDR               0xFFC01E64#define DMA1_9_CURR_X_COUNT            0xFFC01E70#define DMA1_9_CURR_Y_COUNT            0xFFC01E78#define DMA1_9_IRQ_STATUS              0xFFC01E68#define DMA1_9_PERIPHERAL_MAP          0xFFC01E6C#define DMA1_10_CONFIG                 0xFFC01E88#define DMA1_10_NEXT_DESC_PTR          0xFFC01E80#define DMA1_10_START_ADDR             0xFFC01E84#define DMA1_10_X_COUNT                0xFFC01E90#define DMA1_10_Y_COUNT                0xFFC01E98#define DMA1_10_X_MODIFY               0xFFC01E94#define DMA1_10_Y_MODIFY               0xFFC01E9C#define DMA1_10_CURR_DESC_PTR          0xFFC01EA0#define DMA1_10_CURR_ADDR              0xFFC01EA4#define DMA1_10_CURR_X_COUNT           0xFFC01EB0#define DMA1_10_CURR_Y_COUNT           0xFFC01EB8#define DMA1_10_IRQ_STATUS             0xFFC01EA8#define DMA1_10_PERIPHERAL_MAP         0xFFC01EAC#define DMA1_11_CONFIG                 0xFFC01EC8#define DMA1_11_NEXT_DESC_PTR          0xFFC01EC0#define DMA1_11_START_ADDR             0xFFC01EC4#define DMA1_11_X_COUNT                0xFFC01ED0#define DMA1_11_Y_COUNT                0xFFC01ED8#define DMA1_11_X_MODIFY               0xFFC01ED4#define DMA1_11_Y_MODIFY               0xFFC01EDC#define DMA1_11_CURR_DESC_PTR          0xFFC01EE0#define DMA1_11_CURR_ADDR              0xFFC01EE4#define DMA1_11_CURR_X_COUNT           0xFFC01EF0#define DMA1_11_CURR_Y_COUNT           0xFFC01EF8#define DMA1_11_IRQ_STATUS             0xFFC01EE8#define DMA1_11_PERIPHERAL_MAP         0xFFC01EEC#define DMA2_TC_PER                    0xFFC00B0C#define DMA2_TC_CNT                    0xFFC01B10 /* Traffic Control Current Counts */#define DMA2_0_CONFIG                  0xFFC00C08#define DMA2_0_NEXT_DESC_PTR           0xFFC00C00#define DMA2_0_START_ADDR              0xFFC00C04#define DMA2_0_X_COUNT                 0xFFC00C10#define DMA2_0_Y_COUNT                 0xFFC00C18#define DMA2_0_X_MODIFY                0xFFC00C14#define DMA2_0_Y_MODIFY                0xFFC00C1C#define DMA2_0_CURR_DESC_PTR           0xFFC00C20#define DMA2_0_CURR_ADDR               0xFFC00C24#define DMA2_0_CURR_X_COUNT            0xFFC00C30#define DMA2_0_CURR_Y_COUNT            0xFFC00C38#define DMA2_0_IRQ_STATUS              0xFFC00C28#define DMA2_0_PERIPHERAL_MAP          0xFFC00C2C#define DMA2_1_CONFIG                  0xFFC00C48#define DMA2_1_NEXT_DESC_PTR           0xFFC00C40#define DMA2_1_START_ADDR              0xFFC00C44#define DMA2_1_X_COUNT                 0xFFC00C50#define DMA2_1_Y_COUNT                 0xFFC00C58#define DMA2_1_X_MODIFY                0xFFC00C54#define DMA2_1_Y_MODIFY                0xFFC00C5C#define DMA2_1_CURR_DESC_PTR           0xFFC00C60#define DMA2_1_CURR_ADDR               0xFFC00C64#define DMA2_1_CURR_X_COUNT            0xFFC00C70#define DMA2_1_CURR_Y_COUNT            0xFFC00C78#define DMA2_1_IRQ_STATUS              0xFFC00C68#define DMA2_1_PERIPHERAL_MAP          0xFFC00C6C#define DMA2_2_CONFIG                  0xFFC00C88#define DMA2_2_NEXT_DESC_PTR           0xFFC00C80#define DMA2_2_START_ADDR              0xFFC00C84#define DMA2_2_X_COUNT                 0xFFC00C90#define DMA2_2_Y_COUNT                 0xFFC00C98#define DMA2_2_X_MODIFY                0xFFC00C94#define DMA2_2_Y_MODIFY                0xFFC00C9C#define DMA2_2_CURR_DESC_PTR           0xFFC00CA0#define DMA2_2_CURR_ADDR               0xFFC00CA4#define DMA2_2_CURR_X_COUNT            0xFFC00CB0#define DMA2_2_CURR_Y_COUNT            0xFFC00CB8