/* * EBIU Masks */#ifndef __BFIN_PERIPHERAL_EBIU__#define __BFIN_PERIPHERAL_EBIU__/* EBIU_AMGCTL Masks */#define AMCKEN		0x0001		/* Enable CLKOUT */#define AMBEN_NONE	0x0000		/* All Banks Disabled */#define AMBEN_B0	0x0002		/* Enable Asynchronous Memory Bank 0 only */#define AMBEN_B0_B1	0x0004		/* Enable Asynchronous Memory Banks 0 & 1 only */#define AMBEN_B0_B1_B2	0x0006		/* Enable Asynchronous Memory Banks 0,/ 1, and 2 */#define AMBEN_ALL	0x0008		/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */#define B0_PEN		0x0010		/* Enable 16-bit packing Bank 0 */#define B1_PEN		0x0020		/* Enable 16-bit packing Bank 1 */#define B2_PEN		0x0040		/* Enable 16-bit packing Bank 2 */#define B3_PEN		0x0080		/* Enable 16-bit packing Bank 3 */#define CDPRIO		0x0100		/* Core has priority over DMA for external accesses *//* EBIU_AMGCTL Bit Positions */#define AMCKEN_P	0x00000000	/* Enable CLKOUT */#define AMBEN_P0	0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */#define AMBEN_P1	0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */#define AMBEN_P2	0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */#define B0_PEN_P	0x00000004	/* Enable 16-bit packing Bank 0 */#define B1_PEN_P	0x00000005	/* Enable 16-bit packing Bank 1 */#define B2_PEN_P	0x00000006	/* Enable 16-bit packing Bank 2 */#define B3_PEN_P	0x00000007	/* Enable 16-bit packing Bank 3 */#define CDPRIO_P	0x00000008	/* Core has priority over DMA for external accesses *//* EBIU_AMBCTL0 Masks */#define B0RDYEN		0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */#define B0RDYPOL	0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */#define B0TT_1		0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */#define B0TT_2		0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */#define B0TT_3		0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */#define B0TT_4		0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */#define B0ST_1		0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */#define B0ST_2		0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */#define B0ST_3		0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */#define B0ST_4		0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */#define B0HT_1		0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */#define B0HT_2		0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */#define B0HT_3		0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */#define B0HT_0		0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */#define B0RAT_1		0x00000100	/* Bank 0 Read Access Time = 1 cycle */#define B0RAT_2		0x00000200	/* Bank 0 Read Access Time = 2 cycles */#define B0RAT_3		0x00000300	/* Bank 0 Read Access Time = 3 cycles */#define B0RAT_4		0x00000400	/* Bank 0 Read Access Time = 4 cycles */#define B0RAT_5		0x00000500	/* Bank 0 Read Access Time = 5 cycles */#define B0RAT_6		0x00000600	/* Bank 0 Read Access Time = 6 cycles */#define B0RAT_7		0x00000700	/* Bank 0 Read Access Time = 7 cycles */#define B0RAT_8		0x00000800	/* Bank 0 Read Access Time = 8 cycles */#define B0RAT_9		0x00000900	/* Bank 0 Read Access Time = 9 cycles */#define B0RAT_10	0x00000A00	/* Bank 0 Read Access Time = 10 cycles */#define B0RAT_11	0x00000B00	/* Bank 0 Read Access Time = 11 cycles */#define B0RAT_12	0x00000C00	/* Bank 0 Read Access Time = 12 cycles */#define B0RAT_13	0x00000D00	/* Bank 0 Read Access Time = 13 cycles */#define B0RAT_14	0x00000E00	/* Bank 0 Read Access Time = 14 cycles */#define B0RAT_15	0x00000F00	/* Bank 0 Read Access Time = 15 cycles */#define B0WAT_1		0x00001000	/* Bank 0 Write Access Time = 1 cycle */#define B0WAT_2		0x00002000	/* Bank 0 Write Access Time = 2 cycles */#define B0WAT_3		0x00003000	/* Bank 0 Write Access Time = 3 cycles */#define B0WAT_4		0x00004000	/* Bank 0 Write Access Time = 4 cycles */#define B0WAT_5		0x00005000	/* Bank 0 Write Access Time = 5 cycles */#define B0WAT_6		0x00006000	/* Bank 0 Write Access Time = 6 cycles */#define B0WAT_7		0x00007000	/* Bank 0 Write Access Time = 7 cycles */#define B0WAT_8		0x00008000	/* Bank 0 Write Access Time = 8 cycles */#define B0WAT_9		0x00009000	/* Bank 0 Write Access Time = 9 cycles */#define B0WAT_10	0x0000A000	/* Bank 0 Write Access Time = 10 cycles */#define B0WAT_11	0x0000B000	/* Bank 0 Write Access Time = 11 cycles */#define B0WAT_12	0x0000C000	/* Bank 0 Write Access Time = 12 cycles */#define B0WAT_13	0x0000D000	/* Bank 0 Write Access Time = 13 cycles */#define B0WAT_14	0x0000E000	/* Bank 0 Write Access Time = 14 cycles */#define B0WAT_15	0x0000F000	/* Bank 0 Write Access Time = 15 cycles */#define B1RDYEN		0x00010000	/* Bank 1 RDY enable, 0=disable, 1=enable */#define B1RDYPOL	0x00020000	/* Bank 1 RDY Active high, 0=active low, 1=active high */#define B1TT_1		0x00040000	/* Bank 1 Transition Time from Read to Write = 1 cycle */#define B1TT_2		0x00080000	/* Bank 1 Transition Time from Read to Write = 2 cycles */#define B1TT_3		0x000C0000	/* Bank 1 Transition Time from Read to Write = 3 cycles */#define B1TT_4		0x00000000	/* Bank 1 Transition Time from Read to Write = 4 cycles */#define B1ST_1		0x00100000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */#define B1ST_2		0x00200000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */#define B1ST_3		0x00300000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */#define B1ST_4		0x00000000	/* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */#define B1HT_1		0x00400000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */#define B1HT_2		0x00800000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */#define B1HT_3		0x00C00000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */#define B1HT_0		0x00000000	/* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */#define B1RAT_1		0x01000000	/* Bank 1 Read Access Time = 1 cycle */#define B1RAT_2		0x02000000	/* Bank 1 Read Access Time = 2 cycles */#define B1RAT_3		0x03000000	/* Bank 1 Read Access Time = 3 cycles */#define B1RAT_4		0x04000000	/* Bank 1 Read Access Time = 4 cycles */#define B1RAT_5		0x05000000	/* Bank 1 Read Access Time = 5 cycles */#define B1RAT_6		0x06000000	/* Bank 1 Read Access Time = 6 cycles */#define B1RAT_7		0x07000000	/* Bank 1 Read Access Time = 7 cycles */#define B1RAT_8		0x08000000	/* Bank 1 Read Access Time = 8 cycles */#define B1RAT_9		0x09000000	/* Bank 1 Read Access Time = 9 cycles */#define B1RAT_10	0x0A000000	/* Bank 1 Read Access Time = 10 cycles */#define B1RAT_11	0x0B000000	/* Bank 1 Read Access Time = 11 cycles */#define B1RAT_12	0x0C000000	/* Bank 1 Read Access Time = 12 cycles */#define B1RAT_13	0x0D000000	/* Bank 1 Read Access Time = 13 cycles */#define B1RAT_14	0x0E000000	/* Bank 1 Read Access Time = 14 cycles */#define B1RAT_15	0x0F000000	/* Bank 1 Read Access Time = 15 cycles */#define B1WAT_1		0x10000000	/* Bank 1 Write Access Time = 1 cycle */#define B1WAT_2		0x20000000	/* Bank 1 Write Access Time = 2 cycles */#define B1WAT_3		0x30000000	/* Bank 1 Write Access Time = 3 cycles */#define B1WAT_4		0x40000000	/* Bank 1 Write Access Time = 4 cycles */#define B1WAT_5		0x50000000	/* Bank 1 Write Access Time = 5 cycles */#define B1WAT_6		0x60000000	/* Bank 1 Write Access Time = 6 cycles */#define B1WAT_7		0x70000000	/* Bank 1 Write Access Time = 7 cycles */#define B1WAT_8		0x80000000	/* Bank 1 Write Access Time = 8 cycles */#define B1WAT_9		0x90000000	/* Bank 1 Write Access Time = 9 cycles */#define B1WAT_10	0xA0000000	/* Bank 1 Write Access Time = 10 cycles */#define B1WAT_11	0xB0000000	/* Bank 1 Write Access Time = 11 cycles */#define B1WAT_12	0xC0000000	/* Bank 1 Write Access Time = 12 cycles */#define B1WAT_13	0xD0000000	/* Bank 1 Write Access Time = 13 cycles */#define B1WAT_14	0xE0000000	/* Bank 1 Write Access Time = 14 cycles */#define B1WAT_15	0xF0000000	/* Bank 1 Write Access Time = 15 cycles *//* EBIU_AMBCTL1 Masks */#define B2RDYEN		0x00000001	/* Bank 2 RDY Enable, 0=disable, 1=enable */#define B2RDYPOL	0x00000002	/* Bank 2 RDY Active high, 0=active low, 1=active high */#define B2TT_1		0x00000004	/* Bank 2 Transition Time from Read to Write = 1 cycle */#define B2TT_2		0x00000008	/* Bank 2 Transition Time from Read to Write = 2 cycles */#define B2TT_3		0x0000000C	/* Bank 2 Transition Time from Read to Write = 3 cycles */#define B2TT_4		0x00000000	/* Bank 2 Transition Time from Read to Write = 4 cycles */#define B2ST_1		0x00000010	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */#define B2ST_2		0x00000020	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */#define B2ST_3		0x00000030	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */#define B2ST_4		0x00000000	/* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */#define B2HT_1		0x00000040	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */#define B2HT_2		0x00000080	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */#define B2HT_3		0x000000C0	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */#define B2HT_0		0x00000000	/* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */#define B2RAT_1		0x00000100	/* Bank 2 Read Access Time = 1 cycle */#define B2RAT_2		0x00000200	/* Bank 2 Read Access Time = 2 cycles */#define B2RAT_3		0x00000300	/* Bank 2 Read Access Time = 3 cycles */#define B2RAT_4		0x00000400	/* Bank 2 Read Access Time = 4 cycles */#define B2RAT_5		0x00000500	/* Bank 2 Read Access Time = 5 cycles */#define B2RAT_6		0x00000600	/* Bank 2 Read Access Time = 6 cycles */#define B2RAT_7		0x00000700	/* Bank 2 Read Access Time = 7 cycles */#define B2RAT_8		0x00000800	/* Bank 2 Read Access Time = 8 cycles */#define B2RAT_9		0x00000900	/* Bank 2 Read Access Time = 9 cycles */#define B2RAT_10	0x00000A00	/* Bank 2 Read Access Time = 10 cycles */#define B2RAT_11	0x00000B00	/* Bank 2 Read Access Time = 11 cycles */#define B2RAT_12	0x00000C00	/* Bank 2 Read Access Time = 12 cycles */#define B2RAT_13	0x00000D00	/* Bank 2 Read Access Time = 13 cycles */#define B2RAT_14	0x00000E00	/* Bank 2 Read Access Time = 14 cycles */#define B2RAT_15	0x00000F00	/* Bank 2 Read Access Time = 15 cycles */#define B2WAT_1		0x00001000	/* Bank 2 Write Access Time = 1 cycle */#define B2WAT_2		0x00002000	/* Bank 2 Write Access Time = 2 cycles */#define B2WAT_3		0x00003000	/* Bank 2 Write Access Time = 3 cycles */#define B2WAT_4		0x00004000	/* Bank 2 Write Access Time = 4 cycles */#define B2WAT_5		0x00005000	/* Bank 2 Write Access Time = 5 cycles */#define B2WAT_6		0x00006000	/* Bank 2 Write Access Time = 6 cycles */#define B2WAT_7		0x00007000	/* Bank 2 Write Access Time = 7 cycles */#define B2WAT_8		0x00008000	/* Bank 2 Write Access Time = 8 cycles */#define B2WAT_9		0x00009000	/* Bank 2 Write Access Time = 9 cycles */#define B2WAT_10	0x0000A000	/* Bank 2 Write Access Time = 10 cycles */#define B2WAT_11	0x0000B000	/* Bank 2 Write Access Time = 11 cycles */#define B2WAT_12	0x0000C000	/* Bank 2 Write Access Time = 12 cycles */#define B2WAT_13	0x0000D000	/* Bank 2 Write Access Time = 13 cycles */#define B2WAT_14	0x0000E000	/* Bank 2 Write Access Time = 14 cycles */#define B2WAT_15	0x0000F000	/* Bank 2 Write Access Time = 15 cycles */#define B3RDYEN		0x00010000	/* Bank 3 RDY enable, 0=disable, 1=enable */#define B3RDYPOL	0x00020000	/* Bank 3 RDY Active high, 0=active low, 1=active high */#define B3TT_1		0x00040000	/* Bank 3 Transition Time from Read to Write = 1 cycle */#define B3TT_2		0x00080000	/* Bank 3 Transition Time from Read to Write = 2 cycles */#define B3TT_3		0x000C0000	/* Bank 3 Transition Time from Read to Write = 3 cycles */#define B3TT_4		0x00000000	/* Bank 3 Transition Time from Read to Write = 4 cycles */#define B3ST_1		0x00100000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */#define B3ST_2		0x00200000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */#define B3ST_3		0x00300000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */#define B3ST_4		0x00000000	/* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */#define B3HT_1		0x00400000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */#define B3HT_2		0x00800000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */#define B3HT_3		0x00C00000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */#define B3HT_0		0x00000000	/* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */#define B3RAT_1		0x01000000	/* Bank 3 Read Access Time = 1 cycle */#define B3RAT_2		0x02000000	/* Bank 3 Read Access Time = 2 cycles */#define B3RAT_3		0x03000000	/* Bank 3 Read Access Time = 3 cycles */#define B3RAT_4		0x04000000	/* Bank 3 Read Access Time = 4 cycles */#define B3RAT_5		0x05000000	/* Bank 3 Read Access Time = 5 cycles */#define B3RAT_6		0x06000000	/* Bank 3 Read Access Time = 6 cycles */#define B3RAT_7		0x07000000	/* Bank 3 Read Access Time = 7 cycles */#define B3RAT_8		0x08000000	/* Bank 3 Read Access Time = 8 cycles */#define B3RAT_9		0x09000000	/* Bank 3 Read Access Time = 9 cycles */#define B3RAT_10	0x0A000000	/* Bank 3 Read Access Time = 10 cycles */#define B3RAT_11	0x0B000000	/* Bank 3 Read Access Time = 11 cycles */#define B3RAT_12	0x0C000000	/* Bank 3 Read Access Time = 12 cycles */#define B3RAT_13	0x0D000000	/* Bank 3 Read Access Time = 13 cycles */#define B3RAT_14	0x0E000000	/* Bank 3 Read Access Time = 14 cycles */#define B3RAT_15	0x0F000000	/* Bank 3 Read Access Time = 15 cycles */#define B3WAT_1		0x10000000	/* Bank 3 Write Access Time = 1 cycle */#define B3WAT_2		0x20000000	/* Bank 3 Write Access Time = 2 cycles */#define B3WAT_3		0x30000000	/* Bank 3 Write Access Time = 3 cycles */#define B3WAT_4		0x40000000	/* Bank 3 Write Access Time = 4 cycles */#define B3WAT_5		0x50000000	/* Bank 3 Write Access Time = 5 cycles */#define B3WAT_6		0x60000000	/* Bank 3 Write Access Time = 6 cycles */#define B3WAT_7		0x70000000	/* Bank 3 Write Access Time = 7 cycles */#define B3WAT_8		0x80000000	/* Bank 3 Write Access Time = 8 cycles */#define B3WAT_9		0x90000000	/* Bank 3 Write Access Time = 9 cycles */#define B3WAT_10	0xA0000000	/* Bank 3 Write Access Time = 10 cycles */#define B3WAT_11	0xB0000000	/* Bank 3 Write Access Time = 11 cycles */#define B3WAT_12	0xC0000000	/* Bank 3 Write Access Time = 12 cycles */#define B3WAT_13	0xD0000000	/* Bank 3 Write Access Time = 13 cycles */#define B3WAT_14	0xE0000000	/* Bank 3 Write Access Time = 14 cycles */#define B3WAT_15	0xF0000000	/* Bank 3 Write Access Time = 15 cycles *//* Only available on newer parts */#ifdef EBIU_MODE/* EBIU_MBSCTL Bit Positions */#define AMSB0CTL_P	0#define AMSB1CTL_P	2#define AMSB2CTL_P	4#define AMSB3CTL_P	6/* EBIU_MBSCTL Masks */