#define AMSB0CTL_MASK	(0x3 << AMSB0CTL_P)	/* Async Memory Bank 0 Control Modes */#define AMSB0CTL_NONE	(0x0 << AMSB0CTL_P)	/* Control Mode - 00 - No logic */#define AMSB0CTL_ARE	(0x1 << AMSB0CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */#define AMSB0CTL_AOE	(0x2 << AMSB0CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */#define AMSB0CTL_AWE	(0x3 << AMSB0CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */#define AMSB1CTL_MASK	(0x3 << AMSB1CTL_P)	/* Async Memory Bank 1 Control Modes */#define AMSB1CTL_NONE	(0x0 << AMSB1CTL_P)	/* Control Mode - 00 - No logic */#define AMSB1CTL_ARE	(0x1 << AMSB1CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */#define AMSB1CTL_AOE	(0x2 << AMSB1CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */#define AMSB1CTL_AWE	(0x3 << AMSB1CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */#define AMSB2CTL_MASK	(0x3 << AMSB2CTL_P)	/* Async Memory Bank 2 Control Modes */#define AMSB2CTL_NONE	(0x0 << AMSB2CTL_P)	/* Control Mode - 00 - No logic */#define AMSB2CTL_ARE	(0x1 << AMSB2CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */#define AMSB2CTL_AOE	(0x2 << AMSB2CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */#define AMSB2CTL_AWE	(0x3 << AMSB2CTL_P)	/* Control Mode - 03 - OR-ed with /AWE */#define AMSB3CTL_MASK	(0x3 << AMSB3CTL_P)	/* Async Memory Bank 3 Control Modes */#define AMSB3CTL_NONE	(0x0 << AMSB3CTL_P)	/* Control Mode - 00 - No logic */#define AMSB3CTL_ARE	(0x1 << AMSB3CTL_P)	/* Control Mode - 01 - OR-ed with /ARE */#define AMSB3CTL_AOE	(0x2 << AMSB3CTL_P)	/* Control Mode - 02 - OR-ed with /AOE */#define AMSB3CTL_AWE	(0x3 << AMSB3CTL_P)	/* Control Mode - 03 - OR-ed with /AWE *//* EBIU_MODE Bit Positions */#define B0MODE_P	0#define B1MODE_P	2#define B2MODE_P	4#define B3MODE_P	6/* EBIU_MODE Masks */#define B0MODE_MASK	(0x3 << B0MODE_P)	/* Async Memory Bank 0 Access Mode */#define B0MODE_ASYNC	(0x0 << B0MODE_P)	/* Access Mode - 00 - Asynchronous Mode */#define B0MODE_FLASH	(0x1 << B0MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */#define B0MODE_PAGE	(0x2 << B0MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */#define B0MODE_BURST	(0x3 << B0MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */#define B1MODE_MASK	(0x3 << B1MODE_P)	/* Async Memory Bank 1 Access Mode */#define B1MODE_ASYNC	(0x0 << B1MODE_P)	/* Access Mode - 00 - Asynchronous Mode */#define B1MODE_FLASH	(0x1 << B1MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */#define B1MODE_PAGE	(0x2 << B1MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */#define B1MODE_BURST	(0x3 << B1MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */#define B2MODE_MASK	(0x3 << B2MODE_P)	/* Async Memory Bank 2 Access Mode */#define B2MODE_ASYNC	(0x0 << B2MODE_P)	/* Access Mode - 00 - Asynchronous Mode */#define B2MODE_FLASH	(0x1 << B2MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */#define B2MODE_PAGE	(0x2 << B2MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */#define B2MODE_BURST	(0x3 << B2MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode */#define B3MODE_MASK	(0x3 << B3MODE_P)	/* Async Memory Bank 3 Access Mode */#define B3MODE_ASYNC	(0x0 << B3MODE_P)	/* Access Mode - 00 - Asynchronous Mode */#define B3MODE_FLASH	(0x1 << B3MODE_P)	/* Access Mode - 01 - Asynchronous Flash Mode */#define B3MODE_PAGE	(0x2 << B3MODE_P)	/* Access Mode - 10 - Asynchronous Page Mode */#define B3MODE_BURST	(0x3 << B3MODE_P)	/* Access Mode - 11 - Synchronous (Burst) Mode *//* EBIU_FCTL Bit Positions */#define TESTSETLOCK_P	0#define BCLK_P		1#define PGWS_P		3#define PGSZ_P		6#define RDDL_P		7/* EBIU_FCTL Masks */#define TESTSETLOCK	(0x1 << TESTSETLOCK_P)	/* Test set lock */#define BCLK_MASK	(0x3 << BCLK_P)		/* Burst clock frequency */#define BCLK_2		(0x1 << BCLK_P)		/* Burst clock frequency - SCLK/2 */#define BCLK_3		(0x2 << BCLK_P)		/* Burst clock frequency - SCLK/3 */#define BCLK_4		(0x3 << BCLK_P)		/* Burst clock frequency - SCLK/4 */#define PGWS_MASK	(0x7 << PGWS_P)		/* Page wait states */#define PGWS_0		(0x0 << PGWS_P)		/* Page wait states - 0 cycles */#define PGWS_1		(0x1 << PGWS_P)		/* Page wait states - 1 cycles */#define PGWS_2		(0x2 << PGWS_P)		/* Page wait states - 2 cycles */#define PGWS_3		(0x3 << PGWS_P)		/* Page wait states - 3 cycles */#define PGWS_4		(0x4 << PGWS_P)		/* Page wait states - 4 cycles */#define PGSZ		(0x1 << PGSZ_P)		/* Page size */#define PGSZ_4		(0x0 << PGSZ_P)		/* Page size - 4 words */#define PGSZ_8		(0x1 << PGSZ_P)		/* Page size - 8 words */#define RDDL		(0x38 << RDDL_P)	/* Read data delay *//* EBIU_ARBSTAT Masks */#define ARBSTAT		0x00000001	/* Arbitration status */#define BGSTAT		0x00000002	/* External Bus grant status */#endif /* EBIU_MODE *//* Only available on SDRAM based-parts */#ifdef EBIU_SDGCTL/* EBIU_SDGCTL Masks */#define SCTLE		0x00000001	/* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */#define SCK1E		0x00000002	/* Enable CLKOUT, /SCLK1 */#define CL_2		0x00000008	/* SDRAM CAS latency = 2 cycles */#define CL_3		0x0000000C	/* SDRAM CAS latency = 3 cycles */#define PASR_ALL	0x00000000	/* All 4 SDRAM Banks Refreshed In Self-Refresh */#define PASR_B0_B1	0x00000010	/* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */#define PASR_B0		0x00000020	/* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */#define TRAS_1		0x00000040	/* SDRAM tRAS = 1 cycle */#define TRAS_2		0x00000080	/* SDRAM tRAS = 2 cycles */#define TRAS_3		0x000000C0	/* SDRAM tRAS = 3 cycles */#define TRAS_4		0x00000100	/* SDRAM tRAS = 4 cycles */#define TRAS_5		0x00000140	/* SDRAM tRAS = 5 cycles */#define TRAS_6		0x00000180	/* SDRAM tRAS = 6 cycles */#define TRAS_7		0x000001C0	/* SDRAM tRAS = 7 cycles */#define TRAS_8		0x00000200	/* SDRAM tRAS = 8 cycles */#define TRAS_9		0x00000240	/* SDRAM tRAS = 9 cycles */#define TRAS_10		0x00000280	/* SDRAM tRAS = 10 cycles */#define TRAS_11		0x000002C0	/* SDRAM tRAS = 11 cycles */#define TRAS_12		0x00000300	/* SDRAM tRAS = 12 cycles */#define TRAS_13		0x00000340	/* SDRAM tRAS = 13 cycles */#define TRAS_14		0x00000380	/* SDRAM tRAS = 14 cycles */#define TRAS_15		0x000003C0	/* SDRAM tRAS = 15 cycles */#define TRP_1		0x00000800	/* SDRAM tRP = 1 cycle */#define TRP_2		0x00001000	/* SDRAM tRP = 2 cycles */#define TRP_3		0x00001800	/* SDRAM tRP = 3 cycles */#define TRP_4		0x00002000	/* SDRAM tRP = 4 cycles */#define TRP_5		0x00002800	/* SDRAM tRP = 5 cycles */#define TRP_6		0x00003000	/* SDRAM tRP = 6 cycles */#define TRP_7		0x00003800	/* SDRAM tRP = 7 cycles */#define TRCD_1		0x00008000	/* SDRAM tRCD = 1 cycle */#define TRCD_2		0x00010000	/* SDRAM tRCD = 2 cycles */#define TRCD_3		0x00018000	/* SDRAM tRCD = 3 cycles */#define TRCD_4		0x00020000	/* SDRAM tRCD = 4 cycles */#define TRCD_5		0x00028000	/* SDRAM tRCD = 5 cycles */#define TRCD_6		0x00030000	/* SDRAM tRCD = 6 cycles */#define TRCD_7		0x00038000	/* SDRAM tRCD = 7 cycles */#define TWR_1		0x00080000	/* SDRAM tWR = 1 cycle */#define TWR_2		0x00100000	/* SDRAM tWR = 2 cycles */#define TWR_3		0x00180000	/* SDRAM tWR = 3 cycles */#define PUPSD		0x00200000	/* Power-up start delay */#define PSM		0x00400000	/* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */#define PSS		0x00800000	/* enable SDRAM power-up sequence on next SDRAM access */#define SRFS		0x01000000	/* Start SDRAM self-refresh mode */#define EBUFE		0x02000000	/* Enable external buffering timing */#define FBBRW		0x04000000	/* Fast back-to-back read write enable */#define EMREN		0x10000000	/* Extended mode register enable */#define TCSR		0x20000000	/* Temp compensated self refresh value 85 deg C */#define CDDBG		0x40000000	/* Tristate SDRAM controls during bus grant *//* EBIU_SDBCTL Masks */#define EBE		0x0001		/* Enable SDRAM External Bank */#define EBSZ_16		0x0000		/* SDRAM External Bank Size = 16MB */#define EBSZ_32		0x0002		/* SDRAM External Bank Size = 32MB */#define EBSZ_64		0x0004		/* SDRAM External Bank Size = 64MB */#define EBSZ_128	0x0006		/* SDRAM External Bank Size = 128MB */#define EBSZ_256	0x0008		/* SDRAM External Bank Size = 256MB */#define EBSZ_512	0x000A		/* SDRAM External Bank Size = 512MB */#define EBCAW_8		0x0000		/* SDRAM External Bank Column Address Width = 8 Bits */#define EBCAW_9		0x0010		/* SDRAM External Bank Column Address Width = 9 Bits */#define EBCAW_10	0x0020		/* SDRAM External Bank Column Address Width = 10 Bits */#define EBCAW_11	0x0030		/* SDRAM External Bank Column Address Width = 11 Bits */#ifdef __ADSPBF561__#define EB0E		(EBE<<0)	/* Enable SDRAM external bank 0 */#define EB0SZ_16	(EBSZ_16<<0)	/* SDRAM external bank size = 16MB */#define EB0SZ_32	(EBSZ_32<<0)	/* SDRAM external bank size = 32MB */#define EB0SZ_64	(EBSZ_64<<0)	/* SDRAM external bank size = 64MB */#define EB0SZ_128	(EBSZ_128<<0)	/* SDRAM external bank size = 128MB */#define EB0CAW_8	(EBCAW_8<<0)	/* SDRAM external bank column address width = 8 bits */#define EB0CAW_9	(EBCAW_9<<0)	/* SDRAM external bank column address width = 9 bits */#define EB0CAW_10	(EBCAW_10<<0)	/* SDRAM external bank column address width = 9 bits */#define EB0CAW_11	(EBCAW_11<<0)	/* SDRAM external bank column address width = 9 bits */#define EB1E		(EBE<<8)	/* Enable SDRAM external bank 0 */#define EB1SZ_16	(EBSZ_16<<8)	/* SDRAM external bank size = 16MB */#define EB1SZ_32	(EBSZ_32<<8)	/* SDRAM external bank size = 32MB */#define EB1SZ_64	(EBSZ_64<<8)	/* SDRAM external bank size = 64MB */#define EB1SZ_128	(EBSZ_128<<8)	/* SDRAM external bank size = 128MB */#define EB1CAW_8	(EBCAW_8<<8)	/* SDRAM external bank column address width = 8 bits */#define EB1CAW_9	(EBCAW_9<<8)	/* SDRAM external bank column address width = 9 bits */#define EB1CAW_10	(EBCAW_10<<8)	/* SDRAM external bank column address width = 9 bits */#define EB1CAW_11	(EBCAW_11<<8)	/* SDRAM external bank column address width = 9 bits */#define EB2E		(EBE<<16)	/* Enable SDRAM external bank 0 */#define EB2SZ_16	(EBSZ_16<<16)	/* SDRAM external bank size = 16MB */#define EB2SZ_32	(EBSZ_32<<16)	/* SDRAM external bank size = 32MB */#define EB2SZ_64	(EBSZ_64<<16)	/* SDRAM external bank size = 64MB */#define EB2SZ_128	(EBSZ_128<<16)	/* SDRAM external bank size = 128MB */#define EB2CAW_8	(EBCAW_8<<16)	/* SDRAM external bank column address width = 8 bits */#define EB2CAW_9	(EBCAW_9<<16)	/* SDRAM external bank column address width = 9 bits */#define EB2CAW_10	(EBCAW_10<<16)	/* SDRAM external bank column address width = 9 bits */#define EB2CAW_11	(EBCAW_11<<16)	/* SDRAM external bank column address width = 9 bits */#define EB3E		(EBE<<24)	/* Enable SDRAM external bank 0 */#define EB3SZ_16	(EBSZ_16<<24)	/* SDRAM external bank size = 16MB */#define EB3SZ_32	(EBSZ_32<<24)	/* SDRAM external bank size = 32MB */#define EB3SZ_64	(EBSZ_64<<24)	/* SDRAM external bank size = 64MB */#define EB3SZ_128	(EBSZ_128<<24)	/* SDRAM external bank size = 128MB */#define EB3CAW_8	(EBCAW_8<<24)	/* SDRAM external bank column address width = 8 bits */#define EB3CAW_9	(EBCAW_9<<24)	/* SDRAM external bank column address width = 9 bits */#define EB3CAW_10	(EBCAW_10<<24)	/* SDRAM external bank column address width = 9 bits */#define EB3CAW_11	(EBCAW_11<<24)	/* SDRAM external bank column address width = 9 bits */#endif /* BF561 *//* EBIU_SDSTAT Masks */#define SDCI		0x0001		/* SDRAM controller is idle */#define SDSRA		0x0002		/* SDRAM self refresh is active */#define SDPUA		0x0004		/* SDRAM power up active */#define SDRS		0x0008		/* SDRAM is in reset state */#define SDEASE		0x0010		/* SDRAM EAB sticky error status - W1C */#define BGSTAT		0x0020		/* Bus granted *//* Only available on DDR based-parts */#else/* EBIU_ERRMST Masks */#define DEB0_ERROR	0x0001		/* DEB0 access on reserved memory */#define DEB1_ERROR	0x0002		/* DEB1 access on reserved memory */#define DEB2_ERROR	0x0004		/* DEB2 (USB) access on reserved memory */#define CORE_ERROR	0x0008		/* Core access on reserved memory */#define DEB0_MERROR	0x0010		/* DEB0 access on reserved memory and DEB0_ERROR is set */#define DEB1_MERROR	0x0020		/* DEB1 access on reserved memory and DEB1_ERROR is set */#define DEB2_MERROR	0x0040		/* DEB2 access on reserved memory and DEB2_ERROR is set */#define CORE_MERROR	0x0080		/* Core access on reserved memory and CORE_ERROR is set *//* EBIU_RSTCTL Masks */#define DDR_SRESET	0x0001		/* Reset Control to DDR Controller */#define SRREQ		0x0008		/* Self Refresh Request */#define SRACK		0x0010		/* Self Refresh Request Acknowledgement */#define MDDRENABLE	0x0020		/* Mobile DDR Enable */#endif /* EBIU_SDGCTL */#endif