#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register\n */#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)#define pTIMER_ENABLE                  ((uint16_t volatile *)TIMER_ENABLE) /* Timer Enable Register */#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)#define pTIMER_DISABLE                 ((uint16_t volatile *)TIMER_DISABLE) /* Timer Disable Register */#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)#define pTIMER_STATUS                  ((uint32_t volatile *)TIMER_STATUS) /* Timer Status Register */#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)#define pPORTFIO                       ((uint16_t volatile *)PORTFIO) /* Port F I/O Pin State Specify Register */#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)#define pPORTFIO_CLEAR                 ((uint16_t volatile *)PORTFIO_CLEAR) /* Port F I/O Peripheral Interrupt Clear Register */#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)#define pPORTFIO_SET                   ((uint16_t volatile *)PORTFIO_SET) /* Port F I/O Peripheral Interrupt Set Register */#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)#define pPORTFIO_TOGGLE                ((uint16_t volatile *)PORTFIO_TOGGLE) /* Port F I/O Pin State Toggle Register */#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)#define pPORTFIO_MASKA                 ((uint16_t volatile *)PORTFIO_MASKA) /* Port F I/O Mask State Specify Interrupt A Register */#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)#define pPORTFIO_MASKA_CLEAR           ((uint16_t volatile *)PORTFIO_MASKA_CLEAR) /* Port F I/O Mask Disable Interrupt A Register */#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)#define pPORTFIO_MASKA_SET             ((uint16_t volatile *)PORTFIO_MASKA_SET) /* Port F I/O Mask Enable Interrupt A Register */#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)#define pPORTFIO_MASKA_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKA_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt A Register */#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)#define pPORTFIO_MASKB                 ((uint16_t volatile *)PORTFIO_MASKB) /* Port F I/O Mask State Specify Interrupt B Register */#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)#define pPORTFIO_MASKB_CLEAR           ((uint16_t volatile *)PORTFIO_MASKB_CLEAR) /* Port F I/O Mask Disable Interrupt B Register */#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)#define pPORTFIO_MASKB_SET             ((uint16_t volatile *)PORTFIO_MASKB_SET) /* Port F I/O Mask Enable Interrupt B Register */#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)#define pPORTFIO_MASKB_TOGGLE          ((uint16_t volatile *)PORTFIO_MASKB_TOGGLE) /* Port F I/O Mask Toggle Enable Interrupt B Register */#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)#define pPORTFIO_DIR                   ((uint16_t volatile *)PORTFIO_DIR) /* Port F I/O Direction Register */#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)#define pPORTFIO_POLAR                 ((uint16_t volatile *)PORTFIO_POLAR) /* Port F I/O Source Polarity Register */#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)#define pPORTFIO_EDGE                  ((uint16_t volatile *)PORTFIO_EDGE) /* Port F I/O Source Sensitivity Register */#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)#define pPORTFIO_BOTH                  ((uint16_t volatile *)PORTFIO_BOTH) /* Port F I/O Set on BOTH Edges Register */#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)#define pPORTFIO_INEN                  ((uint16_t volatile *)PORTFIO_INEN) /* Port F I/O Input Enable Register  */#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)#define pSPORT0_TCR1                   ((uint16_t volatile *)SPORT0_TCR1) /* SPORT0 Transmit Configuration 1 Register */#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)#define pSPORT0_TCR2                   ((uint16_t volatile *)SPORT0_TCR2) /* SPORT0 Transmit Configuration 2 Register */#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)#define pSPORT0_TCLKDIV                ((uint16_t volatile *)SPORT0_TCLKDIV) /* SPORT0 Transmit Clock Divider */#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)#define pSPORT0_TFSDIV                 ((uint16_t volatile *)SPORT0_TFSDIV) /* SPORT0 Transmit Frame Sync Divider */#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)#define pSPORT0_TX                     ((uint32_t volatile *)SPORT0_TX) /* SPORT0 TX Data Register */#define bfin_read_SPORT0_TX()          bfin_read32(SPORT0_TX)#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)#define pSPORT0_RX                     ((uint32_t volatile *)SPORT0_RX) /* SPORT0 RX Data Register */#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)#define pSPORT0_RCR1                   ((uint16_t volatile *)SPORT0_RCR1) /* SPORT0 Transmit Configuration 1 Register */