/* UART TX Interrupt Masked Erroneously */#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)/* NMI Event at Boot Time Results in Unpredictable State */#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)/* Incorrect Pulse-Width of UART Start Bit */#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)/* Scratchpad Memory Bank Reads May Return Incorrect Data */#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)/* UART STB Bit Incorrectly Affects Receiver Setting */#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)/* SPORT data transmit lines are incorrectly driven in multichannel mode */#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)/* TESTSET operation forces stall on the other core */#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)/* Exception Not Generated for MMR Accesses in Reserved Region */#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)/* Maximum External Clock Speed for Timers */#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)/* ICPLB_STATUS MMR Register May Be Corrupted */#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)/* Stores To Data Cache May Be Lost */#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)/* Hardware Loop Corrupted When Taking an ICPLB Exception */#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)/* IMDMA destination IRQ status must be read prior to using IMDMA */#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)/* IMDMA may corrupt data under certain conditions */#define ANOMALY_05000267 (1)/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */#define ANOMALY_05000269 (1)/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */#define ANOMALY_05000270 (1)/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */#define ANOMALY_05000272 (1)/* Data cache write back to external synchronous memory may be lost */#define ANOMALY_05000274 (1)/* PPI Timing and Sampling Information Updates */#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)/* Disabling Peripherals with DMA Running May Cause DMA System Instability */#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)/* False Hardware Error Exception When ISR Context Is Not Restored */#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */#define ANOMALY_05000283 (1)/* A read will receive incorrect data under certain conditions */#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)/* SPORTs May Receive Bad Data If FIFOs Fill Up */#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */#define ANOMALY_05000301 (1)/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */#define ANOMALY_05000302 (1)/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)/* SCKELOW Bit Does Not Maintain State Through Hibernate */#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */#define ANOMALY_05000310 (1)/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */#define ANOMALY_05000312 (1)/* PPI Is Level-Sensitive on First Transfer */#define ANOMALY_05000313 (1)/* Killed System MMR Write Completes Erroneously On Next System MMR Access */#define ANOMALY_05000315 (1)/* PF2 Output Remains Asserted After SPI Master Boot */#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */#define ANOMALY_05000323 (1)/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */#define ANOMALY_05000357 (1)/* Conflicting Column Address Widths Causes SDRAM Errors */#define ANOMALY_05000362 (1)/* UART Break Signal Issues */#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */#define ANOMALY_05000366 (1)/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */#define ANOMALY_05000371 (1)/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */#define ANOMALY_05000403 (1)/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */#define ANOMALY_05000412 (1)/* Speculative Fetches Can Cause Undesired External FIFO Operations */#define ANOMALY_05000416 (1)/* Multichannel SPORT Channel Misalignment Under Specific Configuration */#define ANOMALY_05000425 (1)/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */#define ANOMALY_05000426 (1)/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */#define ANOMALY_05000443 (1)/* Anomalies that don't exist on this proc */#define ANOMALY_05000158 (0)#define ANOMALY_05000183 (0)#define ANOMALY_05000273 (0)#define ANOMALY_05000311 (0)#define ANOMALY_05000353 (1)#define ANOMALY_05000386 (1)#define ANOMALY_05000432 (0)#define ANOMALY_05000435 (0)#endif