/* * (Cg) Copyright 2007-2008 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com. * Based on board/amcc/sequoia/sequoia.c * * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#include <libfdt.h>#include <fdt_support.h>#include <ppc440.h>#include <asm/processor.h>#include <asm/io.h>#include <asm/bitops.h>#include <command.h>#include <i2c.h>#ifdef CONFIG_RESET_PHY_R#include <miiphy.h>#endif#include <serial.h>#include "fpga.h"#include "pmc440.h"DECLARE_GLOBAL_DATA_PTR;extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */extern void __ft_board_setup(void *blob, bd_t *bd);ulong flash_get_size(ulong base, int banknum);int pci_is_66mhz(void);int is_monarch(void);int bootstrap_eeprom_read(unsigned dev_addr, unsigned offset,			  uchar *buffer, unsigned cnt);struct serial_device *default_serial_console(void){	uchar buf[4];	ulong delay;	int i;	ulong val;	/*	 * Use default console on P4 when strapping jumper	 * is installed (bootstrap option != 'H').	 */	mfsdr(SDR_PINSTP, val);	if (((val & 0xf0000000) >> 29) != 7)		return &serial1_device;	ulong scratchreg = in_be32((void*)GPIO0_ISR3L);	if (!(scratchreg & 0x80)) {		/* mark scratchreg valid */		scratchreg = (scratchreg & 0xffffff00) | 0x80;		i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,					  0x10, buf, 4);		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {			scratchreg |= buf[2];			/* bringup delay for console */			for (delay=0; delay<(1000 * (ulong)buf[3]); delay++) {				udelay(1000);			}		} else			scratchreg |= 0x01;		out_be32((void*)GPIO0_ISR3L, scratchreg);	}	if (scratchreg & 0x01)		return &serial1_device;	else		return &serial0_device;}int board_early_init_f(void){	u32 sdr0_cust0;	u32 sdr0_pfc1, sdr0_pfc2;	u32 reg;	/* general EBC configuration (disable EBC timeouts) */	mtdcr(ebccfga, xbcfg);	mtdcr(ebccfgd, 0xf8400000);	/*	 * Setup the GPIO pins	 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file	 */	out32(GPIO0_OR,    0x40000102);	out32(GPIO0_TCR,   0x4c90011f);	out32(GPIO0_OSRL,  0x28051400);	out32(GPIO0_OSRH,  0x55005000);	out32(GPIO0_TSRL,  0x08051400);	out32(GPIO0_TSRH,  0x55005000);	out32(GPIO0_ISR1L, 0x54000000);	out32(GPIO0_ISR1H, 0x00000000);	out32(GPIO0_ISR2L, 0x44000000);	out32(GPIO0_ISR2H, 0x00000100);	out32(GPIO0_ISR3L, 0x00000000);	out32(GPIO0_ISR3H, 0x00000000);	out32(GPIO1_OR,    0x80002408);	out32(GPIO1_TCR,   0xd6003c08);	out32(GPIO1_OSRL,  0x0a5a0000);	out32(GPIO1_OSRH,  0x00000000);	out32(GPIO1_TSRL,  0x00000000);	out32(GPIO1_TSRH,  0x00000000);	out32(GPIO1_ISR1L, 0x00005555);	out32(GPIO1_ISR1H, 0x40000000);	out32(GPIO1_ISR2L, 0x04010000);	out32(GPIO1_ISR2H, 0x00000000);	out32(GPIO1_ISR3L, 0x01400000);	out32(GPIO1_ISR3H, 0x00000000);	/* patch PLB:PCI divider for 66MHz PCI */	mfcpr(clk_spcid, reg);	if (pci_is_66mhz() && (reg != 0x02000000)) {		mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */		mfcpr(clk_icfg, reg);		reg |= CPR0_ICFG_RLI_MASK;		mtcpr(clk_icfg, reg);		mtspr(dbcr0, 0x20000000); /* do chip reset */	}	/*	 * Setup the interrupt controller polarities, triggers, etc.	 */	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic0er, 0x00000000);	/* disable all */	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */	mtdcr(uic0pr, 0xfffff7ef);	mtdcr(uic0tr, 0x00000000);	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic1sr, 0xffffffff);	/* clear all */	mtdcr(uic1er, 0x00000000);	/* disable all */	mtdcr(uic1cr, 0x00000000);	/* all non-critical */	mtdcr(uic1pr, 0xffffc7f5);	mtdcr(uic1tr, 0x00000000);	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */	mtdcr(uic1sr, 0xffffffff);	/* clear all */	mtdcr(uic2sr, 0xffffffff);	/* clear all */	mtdcr(uic2er, 0x00000000);	/* disable all */	mtdcr(uic2cr, 0x00000000);	/* all non-critical */	mtdcr(uic2pr, 0x27ffffff);	mtdcr(uic2tr, 0x00000000);	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */	mtdcr(uic2sr, 0xffffffff);	/* clear all */	/* select Ethernet pins */	mfsdr(SDR0_PFC1, sdr0_pfc1);	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |		SDR0_PFC1_SELECT_CONFIG_4;	mfsdr(SDR0_PFC2, sdr0_pfc2);	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |		SDR0_PFC2_SELECT_CONFIG_4;	/* enable 2nd IIC */	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;	mtsdr(SDR0_PFC2, sdr0_pfc2);	mtsdr(SDR0_PFC1, sdr0_pfc1);	/* setup NAND FLASH */	mfsdr(SDR0_CUST0, sdr0_cust0);	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|		SDR0_CUST0_NDFC_ENABLE		|		SDR0_CUST0_NDFC_BW_8_BIT	|		SDR0_CUST0_NDFC_ARE_MASK	|		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));	mtsdr(SDR0_CUST0, sdr0_cust0);	return 0;}#if defined(CONFIG_MISC_INIT_F)int misc_init_f(void){	struct pci_controller hose;	hose.first_busno = 0;	hose.last_busno = 0;	hose.region_count = 0;	if (getenv("pciearly") && (!is_monarch())) {		printf("PCI:   early target init\n");		pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA);		pci_target_init(&hose);	}	return 0;}#endif/* * misc_init_r. */int misc_init_r(void){	uint pbcr;	int size_val = 0;	u32 reg;	unsigned long usb2d0cr = 0;	unsigned long usb2phy0cr, usb2h0cr = 0;	unsigned long sdr0_pfc1;	unsigned long sdr0_srst0, sdr0_srst1;	char *act = getenv("usbact");	/*	 * FLASH stuff...	 */	/* Re-do sizing to get full correct info */	/* adjust flash start and offset */	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;	gd->bd->bi_flashoffset = 0;#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)	mtdcr(ebccfga, pb2cr);#else	mtdcr(ebccfga, pb0cr);#endif	pbcr = mfdcr(ebccfgd);	size_val = ffs(gd->bd->bi_flashsize) - 21;	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)	mtdcr(ebccfga, pb2cr);#else	mtdcr(ebccfga, pb0cr);#endif	mtdcr(ebccfgd, pbcr);	/*	 * Re-check to get correct base address	 */	flash_get_size(gd->bd->bi_flashstart, 0);#ifdef CONFIG_ENV_IS_IN_FLASH	/* Monitor protection ON by default */	(void)flash_protect(FLAG_PROTECT_SET,			    -CONFIG_SYS_MONITOR_LEN,			    0xffffffff,			    &flash_info[0]);	/* Env protection ON by default */	(void)flash_protect(FLAG_PROTECT_SET,			    CONFIG_ENV_ADDR_REDUND,			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,			    &flash_info[0]);#endif	/*	 * USB suff...	 */	if ((act == NULL || strcmp(act, "host") == 0) &&	    !(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)){		/* SDR Setting */		mfsdr(SDR0_PFC1, sdr0_pfc1);		mfsdr(SDR0_USB2D0CR, usb2d0cr);		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);		mfsdr(SDR0_USB2H0CR, usb2h0cr);		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*		 * An 8-bit/60MHz interface is the only possible alternative		 * when connecting the Device to the PHY		 */		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;		mtsdr(SDR0_PFC1, sdr0_pfc1);		mtsdr(SDR0_USB2D0CR, usb2d0cr);		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);		mtsdr(SDR0_USB2H0CR, usb2h0cr);		/*		 * Take USB out of reset:		 * -Initial status = all cores are in reset		 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores		 * -wait 1 ms		 * -deassert reset to PHY		 * -wait 1 ms		 * -deassert  reset to HOST		 * -wait 4 ms		 * -deassert all other resets		 */		mfsdr(SDR0_SRST1, sdr0_srst1);		sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 |	\				SDR0_SRST1_P4OPB0 |	\				SDR0_SRST1_OPBA2 |	\				SDR0_SRST1_PLB42OPB1 |	\				SDR0_SRST1_OPB2PLB40);		mtsdr(SDR0_SRST1, sdr0_srst1);		udelay(1000);		mfsdr(SDR0_SRST1, sdr0_srst1);		sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;		mtsdr(SDR0_SRST1, sdr0_srst1);		udelay(1000);		mfsdr(SDR0_SRST0, sdr0_srst0);		sdr0_srst0 &= ~SDR0_SRST0_USB2H;		mtsdr(SDR0_SRST0, sdr0_srst0);		udelay(4000);		/* finally all the other resets */		mtsdr(SDR0_SRST1, 0x00000000);		mtsdr(SDR0_SRST0, 0x00000000);		if (!(in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {			/* enable power on USB socket */			out_be32((void*)GPIO1_OR,				 in_be32((void*)GPIO1_OR) & ~GPIO1_USB_PWR_N);		}		printf("USB:   Host\n");	} else if ((strcmp(act, "dev") == 0) ||		   (in_be32((void*)GPIO0_IR) & GPIO0_USB_PRSNT)) {		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);		udelay (1000);		mtsdr(SDR0_SRST1, 0x672c6000);		udelay (1000);		mtsdr(SDR0_SRST0, 0x00000080);		udelay (1000);		mtsdr(SDR0_SRST1, 0x60206000);		*(unsigned int *)(0xe0000350) = 0x00000001;		udelay (1000);		mtsdr(SDR0_SRST1, 0x60306000);		/* SDR Setting */		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);		mfsdr(SDR0_USB2H0CR, usb2h0cr);		mfsdr(SDR0_USB2D0CR, usb2d0cr);		mfsdr(SDR0_PFC1, sdr0_pfc1);		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;		mtsdr(SDR0_USB2H0CR, usb2h0cr);		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);		mtsdr(SDR0_USB2D0CR, usb2d0cr);		mtsdr(SDR0_PFC1, sdr0_pfc1);		/*clear resets*/		udelay(1000);		mtsdr(SDR0_SRST1, 0x00000000);		udelay(1000);		mtsdr(SDR0_SRST0, 0x00000000);		printf("USB:   Device\n");	}	/*	 * Clear PLB4A0_ACR[WRP]	 * This fix will make the MAL burst disabling patch for the Linux	 * EMAC driver obsolete.	 */	reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;	mtdcr(plb4_acr, reg);#ifdef CONFIG_FPGA	pmc440_init_fpga();#endif	/* turn off POST LED */	out_be32((void*)GPIO1_OR,  in_be32((void*)GPIO1_OR) & ~GPIO1_POST_N);	/* turn on RUN LED */	out_be32((void*)GPIO0_OR,  in_be32((void*)GPIO0_OR) & ~GPIO0_LED_RUN_N);	return 0;}int is_monarch(void){	if (in_be32((void*)GPIO1_IR) & GPIO1_NONMONARCH)		return 0;	return 1;}int pci_is_66mhz(void){	if (in_be32((void*)GPIO1_IR) & GPIO1_M66EN)		return 1;	return 0;}int board_revision(void){	return (int)((in_be32((void*)GPIO1_IR) & GPIO1_HWID_MASK) >> 4);}int checkboard(void){	puts("Board: esd GmbH - PMC440");	gd->board_type = board_revision();	printf(", Rev 1.%ld, ", gd->board_type);	if (!is_monarch()) {		puts("non-");	}	printf("monarch, PCI=%s MHz\n", pci_is_66mhz() ? "66" : "33");	return (0);}#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)/* * Assign interrupts to PCI devices. Some OSs rely on this. */void pmc440_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev){	unsigned char int_line[] = {IRQ_PCIC, IRQ_PCID, IRQ_PCIA, IRQ_PCIB};	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,				   int_line[PCI_DEV(dev) & 0x03]);}#endif