?? and1.vhd
字號:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity AND1 is port
(HZSEL,CR: in std_logic;
AD6,AD5,AD4: out std_logic);
end;
architecture ARC_AND1 of AND1 is
signal dou: std_logic_vector(2 downto 0);
begin
AD6<=dou(2);
AD5<=dou(1);
AD4<=dou(0);
process(HZSEL,CR)
begin
if(CR='0')then
dou<="000";
elsif(HZSEL'event and HZSEL='1')then
if(dou="111")then
dou<="000";
else
dou<=dou+1;
end if;
end if;
end process;
end ARC_AND1;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -