{  GR_REGS,	GR_REGS,	M16_NA_REGS,	M16_NA_REGS,  M16_REGS,	M16_REGS,	M16_REGS,	M16_REGS,  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,  M16_NA_REGS,	M16_NA_REGS,	GR_REGS,	GR_REGS,  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,  T_REG,	GR_REGS,	GR_REGS,	GR_REGS,  GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  FP_REGS,	FP_REGS,	FP_REGS,	FP_REGS,  HI_REG,	LO_REG,		HILO_REG,	ST_REGS,  ST_REGS,	ST_REGS,	ST_REGS,	ST_REGS,  ST_REGS,	ST_REGS,	ST_REGS,	GR_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP0_REGS,	COP0_REGS,	COP0_REGS,	COP0_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP2_REGS,	COP2_REGS,	COP2_REGS,	COP2_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS,  COP3_REGS,	COP3_REGS,	COP3_REGS,	COP3_REGS};/* Map register constraint character to register class.  */enum reg_class mips_char_to_class[256] ={  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,};/* A table describing all the processors gcc knows about.  Names are   matched in the order listed.  The first mention of an ISA level is   taken as the canonical name for that ISA.   To ease comparison, please keep this table in the same order as   gas's mips_cpu_info_table[].  */const struct mips_cpu_info mips_cpu_info_table[] = {  /* Entries for generic ISAs */  { "mips1", PROCESSOR_R3000, 1 },  { "mips2", PROCESSOR_R6000, 2 },  { "mips3", PROCESSOR_R4000, 3 },  { "mips4", PROCESSOR_R8000, 4 },  { "mips32", PROCESSOR_R4KC, 32 },  { "mips64", PROCESSOR_R5KC, 64 },  /* MIPS I */  { "r3000", PROCESSOR_R3000, 1 },  { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */  { "r3900", PROCESSOR_R3900, 1 },  /* MIPS II */  { "r6000", PROCESSOR_R6000, 2 },  /* MIPS III */  { "r4000", PROCESSOR_R4000, 3 },  { "vr4100", PROCESSOR_R4100, 3 },  { "vr4111", PROCESSOR_R4111, 3 },  { "vr4120", PROCESSOR_R4120, 3 },  { "vr4300", PROCESSOR_R4300, 3 },  { "r4400", PROCESSOR_R4000, 3 }, /* = r4000 */  { "r4600", PROCESSOR_R4600, 3 },  { "orion", PROCESSOR_R4600, 3 }, /* = r4600 */  { "r4650", PROCESSOR_R4650, 3 },  /* MIPS IV */  { "r8000", PROCESSOR_R8000, 4 },  { "vr5000", PROCESSOR_R5000, 4 },  { "vr5400", PROCESSOR_R5400, 4 },  { "vr5500", PROCESSOR_R5500, 4 },  /* MIPS 32 */  { "4kc", PROCESSOR_R4KC, 32 },  { "4kp", PROCESSOR_R4KC, 32 }, /* = 4kc */  /* MIPS 64 */  { "5kc", PROCESSOR_R5KC, 64 },  { "20kc", PROCESSOR_R20KC, 64 },  { "sr71000", PROCESSOR_SR71000, 64 },  /* Broadcom SB-1 CPU core */  { "sb1", PROCESSOR_SB1, 64 },  /* End marker */  { 0, 0, 0 }};/* Nonzero if -march should decide the default value of MASK_SOFT_FLOAT.  */#ifndef MIPS_MARCH_CONTROLS_SOFT_FLOAT#define MIPS_MARCH_CONTROLS_SOFT_FLOAT 0#endif/* Initialize the GCC target structure.  */#undef TARGET_ASM_ALIGNED_HI_OP#define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"#undef TARGET_ASM_ALIGNED_SI_OP#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"#undef TARGET_ASM_INTEGER#define TARGET_ASM_INTEGER mips_assemble_integer#if TARGET_IRIX5 && !TARGET_IRIX6#undef TARGET_ASM_UNALIGNED_HI_OP#define TARGET_ASM_UNALIGNED_HI_OP "\t.align 0\n\t.half\t"#undef TARGET_ASM_UNALIGNED_SI_OP#define TARGET_ASM_UNALIGNED_SI_OP "\t.align 0\n\t.word\t"/* The IRIX 6 O32 assembler gives an error for `align 0; .dword', contrary   to the documentation, so disable it.  */#undef TARGET_ASM_UNALIGNED_DI_OP#define TARGET_ASM_UNALIGNED_DI_OP NULL#endif#undef TARGET_ASM_FUNCTION_PROLOGUE#define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue#undef TARGET_ASM_FUNCTION_EPILOGUE#define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue#undef TARGET_ASM_SELECT_RTX_SECTION#define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section#undef TARGET_SCHED_ADJUST_COST#define TARGET_SCHED_ADJUST_COST mips_adjust_cost#undef TARGET_SCHED_ISSUE_RATE#define TARGET_SCHED_ISSUE_RATE mips_issue_rate#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface#undef TARGET_ENCODE_SECTION_INFO#define TARGET_ENCODE_SECTION_INFO mips_encode_section_infostruct gcc_target targetm = TARGET_INITIALIZER;/* Return truth value of whether OP can be used as an operands   where a register or 16 bit unsigned integer is needed.  */intuns_arith_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))    return 1;  return register_operand (op, mode);}/* Return truth value of whether OP can be used as an operands   where a 16 bit integer is needed  */intarith_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (GET_CODE (op) == CONST_INT && SMALL_INT (op))    return 1;  /* On the mips16, a GP relative value is a signed 16 bit offset.  */  if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))    return 1;  return register_operand (op, mode);}/* Return truth value of whether OP can be used as an operand in a two   address arithmetic insn (such as set 123456,%o4) of mode MODE.  */intarith32_operand (op, mode)     rtx op;     enum machine_mode mode;{  if (GET_CODE (op) == CONST_INT)    return 1;  return register_operand (op, mode);}/* Return truth value of whether OP is an integer which fits in 16 bits.  */intsmall_int (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  return (GET_CODE (op) == CONST_INT && SMALL_INT (op));}/* Return truth value of whether OP is a 32 bit integer which is too big to   be loaded with one instruction.  */intlarge_int (op, mode)     rtx op;     enum machine_mode mode ATTRIBUTE_UNUSED;{  HOST_WIDE_INT value;  if (GET_CODE (op) != CONST_INT)    return 0;  value = INTVAL (op);  /* ior reg,$r0,value */  if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)    return 0;  /* subu reg,$r0,value */  if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)    return 0;  /* lui reg,value>>16 */  if ((value & 0x0000ffff) == 0)    return 0;  return 1;}/* Return truth value of whether OP is a register or the constant 0.   In mips16 mode, we only accept a register, since the mips16 does   not have $0.  */intreg_or_0_operand (op, mode)     rtx op;     enum machine_mode mode;{  switch (GET_CODE (op))    {    case CONST_INT:      if (TARGET_MIPS16)	return 0;      return INTVAL (op) == 0;    case CONST_DOUBLE:      if (TARGET_MIPS16)	return 0;      return op == CONST0_RTX (mode);    case REG:    case SUBREG:      return register_operand (op, mode);    default:      break;    }  return 0;}/* Return truth value of whether OP is a register or the constant 0,   even in mips16 mode.  */inttrue_reg_or_0_operand (op, mode)     rtx op;     enum machine_mode mode;{  switch (GET_CODE (op))    {    case CONST_INT:      return INTVAL (op) == 0;    case CONST_DOUBLE:      return op == CONST0_RTX (mode);    case REG:    case SUBREG:      return register_operand (op, mode);    default:      break;    }  return 0;}/* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */intmips_const_double_ok (op, mode)     rtx op;     enum machine_mode mode;{  if (GET_CODE (op) != CONST_DOUBLE)    return 0;  if (mode == VOIDmode)    return 1;  /* We've no zero register in mips16 mode.  */  if (TARGET_MIPS16)    return 0;  if (mode != SFmode && mode != DFmode)    return 0;  if (op == CONST0_RTX (mode))    return 1;  return 0;}/* Accept the floating point constant 1 in the appropriate mode.  */intconst_float_1_operand (op, mode)     rtx op;     enum machine_mode mode;{  REAL_VALUE_TYPE d;  if (GET_CODE (op) != CONST_DOUBLE      || mode != GET_MODE (op)      || (mode != DFmode && mode != SFmode))    return 0;  REAL_VALUE_FROM_CONST_DOUBLE (d, op);  return REAL_VALUES_EQUAL (d, dconst1);}/* Return true if a memory load or store of REG plus OFFSET in MODE   can be represented in a single word on the mips16.  */static intmips16_simple_memory_operand (reg, offset, mode)     rtx reg;     rtx offset;     enum machine_mode mode;{  unsigned int size;  int off;  if (mode == BLKmode)    {      /* We can't tell, because we don't know how the value will         eventually be accessed.  Returning 0 here does no great         harm; it just prevents some possible instruction scheduling.  */      return 0;    }  size = GET_MODE_SIZE (mode);  if (INTVAL (offset) % size != 0)    return 0;  if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)    off = 0x100;  else    off = 0x20;  if (INTVAL (offset) >= 0 && INTVAL (offset) < (HOST_WIDE_INT)(off * size))    return 1;  return 0;}/* Return truth value if a memory operand fits in a single instruction   (ie, register + small offset).  */intsimple_memory_operand (op, mode)     rtx op;     enum machine_mode mode;{  rtx addr, plus0, plus1;  /* Eliminate non-memory operations */  if (GET_CODE (op) != MEM)    return 0;  /* dword operations really put out 2 instructions, so eliminate them.  */  /* ??? This isn't strictly correct.  It is OK to accept multiword modes