;;- Machine description for ARM for GNU compiler;;  Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000,;;  2001, 2002, 2004  Free Software Foundation, Inc.;;  Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl);;  and Martin Simmons (@harleqn.co.uk).;;  More major hacks by Richard Earnshaw (rearnsha@arm.com).;; This file is part of GNU CC.;; GNU CC is free software; you can redistribute it and/or modify;; it under the terms of the GNU General Public License as published by;; the Free Software Foundation; either version 2, or (at your option);; any later version.;; GNU CC is distributed in the hope that it will be useful,;; but WITHOUT ANY WARRANTY; without even the implied warranty of;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the;; GNU General Public License for more details.;; You should have received a copy of the GNU General Public License;; along with GNU CC; see the file COPYING.  If not, write to;; the Free Software Foundation, 59 Temple Place - Suite 330,;; Boston, MA 02111-1307, USA.;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.;; There are patterns in this file to support XFmode arithmetic.;; Unfortunately RISC iX doesn't work well with these so they are disabled.;; (See arm.h);;---------------------------------------------------------------------------;; Constants;; Register numbers(define_constants  [(IP_REGNUM	    12)		; Scratch register   (SP_REGNUM	    13)		; Stack pointer   (LR_REGNUM       14)		; Return address register   (PC_REGNUM	    15)		; Program counter   (CC_REGNUM       24)		; Condition code pseudo register   (LAST_ARM_REGNUM 15)  ]);; UNSPEC Usage:;; Note: sin and cos are no-longer used.(define_constants  [(UNSPEC_SIN       0)	; `sin' operation (MODE_FLOAT):			;   operand 0 is the result,			;   operand 1 the parameter.   (UNPSEC_COS	     1)	; `cos' operation (MODE_FLOAT):			;   operand 0 is the result,			;   operand 1 the parameter.   (UNSPEC_PUSH_MULT 2)	; `push multiple' operation:			;   operand 0 is the first register,			;   subsequent registers are in parallel (use ...)			;   expressions.   (UNSPEC_PIC_SYM   3) ; A symbol that has been treated properly for pic			;   usage, that is, we will add the pic_register			;   value to it before trying to dereference it.   (UNSPEC_PIC_BASE  4)	; Adding the PC value to the offset to the			;   GLOBAL_OFFSET_TABLE.  The operation is fully			;   described by the RTL but must be wrapped to			;   prevent combine from trying to rip it apart.   (UNSPEC_PRLG_STK  5) ; A special barrier that prevents frame accesses 			;   being scheduled before the stack adjustment insn.   (UNSPEC_CLZ	     5) ; `clz' instruction, count leading zeros (SImode):			;   operand 0 is the result,			;   operand 1 is the parameter.   (UNSPEC_PROLOGUE_USE 6) ; As USE insns are not meaningful after reload,   			; this unspec is used to prevent the deletion of   			; instructions setting registers for EH handling   			; and stack frame generation.  Operand 0 is the   			; register to "use".   (UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.  ]);; UNSPEC_VOLATILE Usage:(define_constants  [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an			;   insn in the code.   (VUNSPEC_EPILOGUE 1) ; `epilogue' insn, used to represent any part of the			;   instruction epilogue sequence that isn't expanded			;   into normal RTL.  Used for both normal and sibcall			;   epilogues.   (VUNSPEC_ALIGN    2) ; `align' insn.  Used at the head of a minipool table 			;   for inlined constants.   (VUNSPEC_POOL_END 3) ; `end-of-table'.  Used to mark the end of a minipool			;   table.   (VUNSPEC_POOL_1   4) ; `pool-entry(1)'.  An entry in the constant pool for			;   an 8-bit object.   (VUNSPEC_POOL_2   5) ; `pool-entry(2)'.  An entry in the constant pool for			;   a 16-bit object.   (VUNSPEC_POOL_4   6) ; `pool-entry(4)'.  An entry in the constant pool for			;   a 32-bit object.   (VUNSPEC_POOL_8   7) ; `pool-entry(8)'.  An entry in the constant pool for			;   a 64-bit object.  ]);;---------------------------------------------------------------------------;; Attributes; IS_THUMB is set to 'yes' when we are generating Thumb code, and 'no' when; generating ARM code.  This is used to control the length of some insn; patterns that share the same RTL in both ARM and Thumb code.(define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code"))); PROG_MODE attribute is used to determine whether condition codes are; clobbered by a call insn: they are if in prog32 mode.  This is controlled; by the -mapcs-{32,26} flag, and possibly the -mcpu=... option.(define_attr "prog_mode" "prog26,prog32" (const (symbol_ref "arm_prog_mode"))); IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects; scheduling decisions for the load unit and the multiplier.(define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_is_strong")));; Operand number of an input operand that is shifted.  Zero if the;; given instruction does not shift one of its input operands.(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale")))(define_attr "shift" "" (const_int 0)); Floating Point Unit.  If we only have floating point emulation, then there; is no point in scheduling the floating point insns.  (Well, for best; performance we should try and group them together).(define_attr "fpu" "fpa,fpe2,fpe3" (const (symbol_ref "arm_fpu_attr"))); LENGTH of an instruction (in bytes)(define_attr "length" "" (const_int 4)); POOL_RANGE is how far away from a constant pool entry that this insn; can be placed.  If the distance is zero, then this insn will never; reference the pool.; NEG_POOL_RANGE is nonzero for insns that can reference a constant pool entry; before its address.(define_attr "pool_range" "" (const_int 0))(define_attr "neg_pool_range" "" (const_int 0)); An assembler sequence may clobber the condition codes without us knowing.; If such an insn references the pool, then we have no way of knowing how,; so use the most conservative value for pool_range.(define_asm_attributes [(set_attr "conds" "clob")  (set_attr "length" "4")  (set_attr "pool_range" "250")]); TYPE attribute is used to detect floating point instructions which, if; running on a co-processor can run in parallel with other, basic instructions; If write-buffer scheduling is enabled then it can also be used in the; scheduling of writes.; Classification of each insn; normal	any data instruction that doesn't hit memory or fp regs; mult		a multiply instruction; block		blockage insn, this blocks all functional units; float		a floating point arithmetic operation (subject to expansion); fdivx		XFmode floating point division; fdivd		DFmode floating point division; fdivs		SFmode floating point division; fmul		Floating point multiply; ffmul		Fast floating point multiply; farith	Floating point arithmetic (4 cycle); ffarith	Fast floating point arithmetic (2 cycle); float_em	a floating point arithmetic operation that is normally emulated;		even on a machine with an fpa.; f_load	a floating point load from memory; f_store	a floating point store to memory; f_mem_r	a transfer of a floating point register to a real reg via mem; r_mem_f	the reverse of f_mem_r; f_2_r		fast transfer float to arm (no memory needed); r_2_f		fast transfer arm to float; call		a subroutine call; load		any load from memory; store1	store 1 word to memory from arm registers; store2	store 2 words; store3	store 3 words; store4	store 4 words;(define_attr "type"	"normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4" 	(const_string "normal")); Load scheduling, set from the arm_ld_sched variable; initialized by arm_override_options() (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched"))); condition codes: this one is used by final_prescan_insn to speed up; conditionalizing instructions.  It saves having to scan the rtl to see if; it uses or alters the condition codes.; ; USE means that the condition codes are used by the insn in the process of;   outputting code, this means (at present) that we can't use the insn in;   inlined branches;; SET means that the purpose of the insn is to set the condition codes in a;   well defined manner.;; CLOB means that the condition codes are altered in an undefined manner, if;   they are altered at all;; JUMP_CLOB is used when the condition cannot be represented by a single;   instruction (UNEQ and LTGT).  These cannot be predicated.;; NOCOND means that the condition codes are neither altered nor affect the;   output of this insn(define_attr "conds" "use,set,clob,jump_clob,nocond"	(if_then_else (eq_attr "type" "call")	 (if_then_else (eq_attr "prog_mode" "prog32")	  (const_string "clob") (const_string "nocond"))	 (const_string "nocond"))); Predicable means that the insn can be conditionally executed based on; an automatically added predicate (additional patterns are generated by ; gen...).  We default to 'no' because no Thumb patterns match this rule; and not all ARM patterns do.(define_attr "predicable" "no,yes" (const_string "no")); Only model the write buffer for ARM6 and ARM7.  Earlier processors don't; have one.  Later ones, such as StrongARM, have write-back caches, so don't; suffer blockages enough to warrent modelling this (and it can adversely; affect the schedule).(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7"))); WRITE_CONFLICT implies that a read following an unrelated write is likely; to stall the processor.  Used with model_wbuf above.(define_attr "write_conflict" "no,yes"  (if_then_else (eq_attr "type"		 "block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load")		(const_string "yes")		(const_string "no"))); Classify the insns into those that take one cycle and those that take more; than one on the main cpu execution unit.(define_attr "core_cycles" "single,multi"  (if_then_else (eq_attr "type"		 "normal,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith")		(const_string "single")	        (const_string "multi")));; FAR_JUMP is "yes" if a BL instruction is used to generate a branch to a;; distant label.  Only applicable to Thumb code.(define_attr "far_jump" "yes,no" (const_string "no"));; (define_function_unit {name} {num-units} {n-users} {test};;                       {ready-delay} {issue-delay} [{conflict-list}]);;--------------------------------------------------------------------;; Floating point unit (FPA);;--------------------------------------------------------------------(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "fdivx")) 71 69)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "fdivd")) 59 57)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "fdivs")) 31 29)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "fmul")) 9 7)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "ffmul")) 6 4)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "farith")) 4 2)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "ffarith")) 2 2)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "r_2_f")) 5 3)(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa")				     (eq_attr "type" "f_2_r")) 1 2); The fpa10 doesn't really have a memory read unit, but it can start to; speculatively execute the instruction in the pipeline, provided the data; is already loaded, so pretend reads have a delay of 2 (and that the; pipeline is infinite).(define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa")					 (eq_attr "type" "f_load")) 3 1);;--------------------------------------------------------------------;; Write buffer;;--------------------------------------------------------------------; Strictly, we should model a 4-deep write buffer for ARM7xx based chips;; The write buffer on some of the arm6 processors is hard to model exactly.; There is room in the buffer for up to two addresses and up to eight words; of memory, but the two needn't be split evenly.  When writing the two; addresses are fully pipelined.  However, a read from memory that is not; currently in the cache will block until the writes have completed.; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous; (they aren't allowed to be at present) then there is a startup cost of 1MCLK; cycle to add as well.(define_function_unit "write_buf" 1 2  (and (eq_attr "model_wbuf" "yes")       (eq_attr "type" "store1,r_mem_f")) 5 3)(define_function_unit "write_buf" 1 2   (and (eq_attr "model_wbuf" "yes")       (eq_attr "type" "store2")) 7 4)(define_function_unit "write_buf" 1 2  (and (eq_attr "model_wbuf" "yes")       (eq_attr "type" "store3")) 9 5)(define_function_unit "write_buf" 1 2  (and (eq_attr "model_wbuf" "yes")       (eq_attr "type" "store4")) 11 6);;--------------------------------------------------------------------;; Write blockage unit;;--------------------------------------------------------------------; The write_blockage unit models (partially), the fact that reads will stall; until the write buffer empties.; The f_mem_r and r_mem_f could also block, but they are to the stack,; so we don't model them here(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes")						(eq_attr "type" "store1")) 5 5	[(eq_attr "write_conflict" "yes")])(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes")						(eq_attr "type" "store2")) 7 7	[(eq_attr "write_conflict" "yes")])(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes")						(eq_attr "type" "store3")) 9 9	[(eq_attr "write_conflict" "yes")])(define_function_unit "write_blockage" 1 0	(and (eq_attr "model_wbuf" "yes") (eq_attr "type" "store4")) 11 11	[(eq_attr "write_conflict" "yes")])(define_function_unit "write_blockage" 1 0	(and (eq_attr "model_wbuf" "yes")	     (eq_attr "write_conflict" "yes")) 1 1);;--------------------------------------------------------------------;; Core unit;;--------------------------------------------------------------------; Everything must spend at least one cycle in the core unit(define_function_unit "core" 1 0 (eq_attr "core_cycles" "single") 1 1)(define_function_unit "core" 1 0  (and (eq_attr "ldsched" "yes") (eq_attr "type" "store1")) 1 1)(define_function_unit "core" 1 0  (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) 2 1);; We do not need to conditionalize the define_function_unit immediately;; above.  This one will be ignored for anything other than xscale;; compiles and for xscale compiles it provides a larger delay;; and the scheduler will DTRT.;; FIXME: this test needs to be revamped to not depend on this feature ;; of the scheduler.(define_function_unit "core" 1 0  (and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load"))       (eq_attr "is_xscale" "yes"))   3 1)(define_function_unit "core" 1 0  (and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1")) 2 2)(define_function_unit "core" 1 0  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load")) 3 3)(define_function_unit "core" 1 0  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store")) 4 4)(define_function_unit "core" 1 0  (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")) 6 6)(define_function_unit "core" 1 0  (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r")) 7 7)(define_function_unit "core" 1 0  (and (eq_attr "ldsched" "no") (eq_attr "type" "mult")) 16 16)(define_function_unit "core" 1 0  (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no"))       (eq_attr "type" "mult")) 4 4)(define_function_unit "core" 1 0  (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "yes"))       (eq_attr "type" "mult")) 3 2)