/* Definitions of target machine for GNU compiler, for DEC Alpha.   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,   2000, 2001, 2002 Free Software Foundation, Inc.   Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)This file is part of GNU CC.GNU CC is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2, or (at your option)any later version.GNU CC is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with GNU CC; see the file COPYING.  If not, write tothe Free Software Foundation, 59 Temple Place - Suite 330,Boston, MA 02111-1307, USA.  *//* Target CPU builtins.  */#define TARGET_CPU_CPP_BUILTINS()			\  do							\    {							\	builtin_define ("__alpha");			\	builtin_define ("__alpha__");			\	builtin_assert ("cpu=alpha");			\	builtin_assert ("machine=alpha");		\	if (TARGET_CIX)					\	  {						\	    builtin_define ("__alpha_cix__");		\	    builtin_assert ("cpu=cix");			\	  }						\	if (TARGET_FIX)					\	  {						\	    builtin_define ("__alpha_fix__");		\	    builtin_assert ("cpu=fix");			\	  }						\	if (TARGET_BWX)					\	  {						\	    builtin_define ("__alpha_bwx__");		\	    builtin_assert ("cpu=bwx");			\	  }						\	if (TARGET_MAX)					\	  {						\	    builtin_define ("__alpha_max__");		\	    builtin_assert ("cpu=max");			\	  }						\	if (TARGET_CPU_EV6)				\	  {						\	    builtin_define ("__alpha_ev6__");		\	    builtin_assert ("cpu=ev6");			\	  }						\	else if (TARGET_CPU_EV5)			\	  {						\	    builtin_define ("__alpha_ev5__");		\	    builtin_assert ("cpu=ev5");			\	  }						\	else	/* Presumably ev4.  */			\	  {						\	    builtin_define ("__alpha_ev4__");		\	    builtin_assert ("cpu=ev4");			\	  }						\	if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT)	\	  builtin_define ("_IEEE_FP");			\	if (TARGET_IEEE_WITH_INEXACT)			\	  builtin_define ("_IEEE_FP_INEXACT");		\	if (TARGET_LONG_DOUBLE_128)			\	  builtin_define ("__LONG_DOUBLE_128__");	\							\	/* Macros dependent on the C dialect.  */	\	SUBTARGET_LANGUAGE_CPP_BUILTINS();		\} while (0)#ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS#define SUBTARGET_LANGUAGE_CPP_BUILTINS()		\  do							\    {							\      if (preprocessing_asm_p ())			\	builtin_define_std ("LANGUAGE_ASSEMBLY");	\      else if (c_language == clk_c)			\	builtin_define_std ("LANGUAGE_C");		\      else if (c_language == clk_cplusplus)		\	{						\	  builtin_define ("__LANGUAGE_C_PLUS_PLUS");	\	  builtin_define ("__LANGUAGE_C_PLUS_PLUS__");	\	}						\      if (flag_objc)					\	{						\	  builtin_define ("__LANGUAGE_OBJECTIVE_C");	\	  builtin_define ("__LANGUAGE_OBJECTIVE_C__");	\	}						\    }							\  while (0)#endif#define CPP_SPEC "%(cpp_subtarget)"#ifndef CPP_SUBTARGET_SPEC#define CPP_SUBTARGET_SPEC ""#endif#define WORD_SWITCH_TAKES_ARG(STR)		\ (!strcmp (STR, "rpath") || DEFAULT_WORD_SWITCH_TAKES_ARG(STR))/* Print subsidiary information on the compiler version in use.  */#define TARGET_VERSION/* Run-time compilation parameters selecting different hardware subsets.  *//* Which processor to schedule for. The cpu attribute defines a list that   mirrors this list, so changes to alpha.md must be made at the same time.  */enum processor_type {PROCESSOR_EV4,			/* 2106[46]{a,} */  PROCESSOR_EV5,			/* 21164{a,pc,} */  PROCESSOR_EV6};			/* 21264 */extern enum processor_type alpha_cpu;enum alpha_trap_precision{  ALPHA_TP_PROG,	/* No precision (default).  */  ALPHA_TP_FUNC,      	/* Trap contained within originating function.  */  ALPHA_TP_INSN		/* Instruction accuracy and code is resumption safe.  */};enum alpha_fp_rounding_mode{  ALPHA_FPRM_NORM,	/* Normal rounding mode.  */  ALPHA_FPRM_MINF,	/* Round towards minus-infinity.  */  ALPHA_FPRM_CHOP,	/* Chopped rounding mode (towards 0).  */  ALPHA_FPRM_DYN	/* Dynamic rounding mode.  */};enum alpha_fp_trap_mode{  ALPHA_FPTM_N,		/* Normal trap mode.  */  ALPHA_FPTM_U,		/* Underflow traps enabled.  */  ALPHA_FPTM_SU,	/* Software completion, w/underflow traps */  ALPHA_FPTM_SUI	/* Software completion, w/underflow & inexact traps */};extern int target_flags;extern enum alpha_trap_precision alpha_tp;extern enum alpha_fp_rounding_mode alpha_fprm;extern enum alpha_fp_trap_mode alpha_fptm;extern int alpha_tls_size;/* This means that floating-point support exists in the target implementation   of the Alpha architecture.  This is usually the default.  */#define MASK_FP		(1 << 0)#define TARGET_FP	(target_flags & MASK_FP)/* This means that floating-point registers are allowed to be used.  Note   that Alpha implementations without FP operations are required to   provide the FP registers.  */#define MASK_FPREGS	(1 << 1)#define TARGET_FPREGS	(target_flags & MASK_FPREGS)/* This means that gas is used to process the assembler file.  */#define MASK_GAS	(1 << 2)#define TARGET_GAS	(target_flags & MASK_GAS)/* This means that we should mark procedures as IEEE conformant.  */#define MASK_IEEE_CONFORMANT (1 << 3)#define TARGET_IEEE_CONFORMANT	(target_flags & MASK_IEEE_CONFORMANT)/* This means we should be IEEE-compliant except for inexact.  */#define MASK_IEEE	(1 << 4)#define TARGET_IEEE	(target_flags & MASK_IEEE)/* This means we should be fully IEEE-compliant.  */#define MASK_IEEE_WITH_INEXACT (1 << 5)#define TARGET_IEEE_WITH_INEXACT (target_flags & MASK_IEEE_WITH_INEXACT)/* This means we must construct all constants rather than emitting   them as literal data.  */#define MASK_BUILD_CONSTANTS (1 << 6)#define TARGET_BUILD_CONSTANTS (target_flags & MASK_BUILD_CONSTANTS)/* This means we handle floating points in VAX F- (float)   or G- (double) Format.  */#define MASK_FLOAT_VAX	(1 << 7)#define TARGET_FLOAT_VAX (target_flags & MASK_FLOAT_VAX)/* This means that the processor has byte and half word loads and stores   (the BWX extension).  */#define MASK_BWX	(1 << 8)#define TARGET_BWX	(target_flags & MASK_BWX)/* This means that the processor has the MAX extension.  */#define MASK_MAX	(1 << 9)#define TARGET_MAX	(target_flags & MASK_MAX)/* This means that the processor has the FIX extension.  */#define MASK_FIX	(1 << 10)#define TARGET_FIX	(target_flags & MASK_FIX)/* This means that the processor has the CIX extension.  */#define MASK_CIX	(1 << 11)#define TARGET_CIX	(target_flags & MASK_CIX)/* This means use !literal style explicit relocations.  */#define MASK_EXPLICIT_RELOCS (1 << 12)#define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)/* This means use 16-bit relocations to .sdata/.sbss.  */#define MASK_SMALL_DATA (1 << 13)#define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA)/* This means emit thread pointer loads for kernel not user.  */#define MASK_TLS_KERNEL	(1 << 14)#define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL)/* This means use IEEE quad-format for long double.  Assumes the    presence of the GEM support library routines.  */#define MASK_LONG_DOUBLE_128 (1 << 16)#define TARGET_LONG_DOUBLE_128 (target_flags & MASK_LONG_DOUBLE_128)/* This means that the processor is an EV5, EV56, or PCA56.   Unlike alpha_cpu this is not affected by -mtune= setting.  */#define MASK_CPU_EV5	(1 << 28)#define TARGET_CPU_EV5	(target_flags & MASK_CPU_EV5)/* Likewise for EV6.  */#define MASK_CPU_EV6	(1 << 29)#define TARGET_CPU_EV6	(target_flags & MASK_CPU_EV6)/* This means we support the .arch directive in the assembler.  Only   defined in TARGET_CPU_DEFAULT.  */#define MASK_SUPPORT_ARCH (1 << 30)#define TARGET_SUPPORT_ARCH	(target_flags & MASK_SUPPORT_ARCH)/* These are for target os support and cannot be changed at runtime.  */#define TARGET_ABI_WINDOWS_NT 0#define TARGET_ABI_OPEN_VMS 0#define TARGET_ABI_UNICOSMK 0#define TARGET_ABI_OSF (!TARGET_ABI_WINDOWS_NT	\			&& !TARGET_ABI_OPEN_VMS	\			&& !TARGET_ABI_UNICOSMK)#ifndef TARGET_AS_CAN_SUBTRACT_LABELS#define TARGET_AS_CAN_SUBTRACT_LABELS TARGET_GAS#endif#ifndef TARGET_AS_SLASH_BEFORE_SUFFIX#define TARGET_AS_SLASH_BEFORE_SUFFIX TARGET_GAS#endif#ifndef TARGET_CAN_FAULT_IN_PROLOGUE#define TARGET_CAN_FAULT_IN_PROLOGUE 0#endif#ifndef TARGET_HAS_XFLOATING_LIBS#define TARGET_HAS_XFLOATING_LIBS TARGET_LONG_DOUBLE_128#endif#ifndef TARGET_PROFILING_NEEDS_GP#define TARGET_PROFILING_NEEDS_GP 0#endif#ifndef TARGET_LD_BUGGY_LDGP#define TARGET_LD_BUGGY_LDGP 0#endif#ifndef TARGET_FIXUP_EV5_PREFETCH#define TARGET_FIXUP_EV5_PREFETCH 0#endif#ifndef HAVE_AS_TLS#define HAVE_AS_TLS 0#endif/* Macro to define tables used to set the flags.   This is a list in braces of pairs in braces,   each pair being { "NAME", VALUE }   where VALUE is the bits to set or minus the bits to clear.   An empty string NAME is used to identify the default VALUE.  */#define TARGET_SWITCHES							\  { {"no-soft-float", MASK_FP, N_("Use hardware fp")},			\    {"soft-float", - MASK_FP, N_("Do not use hardware fp")},		\    {"fp-regs", MASK_FPREGS, N_("Use fp registers")},			\    {"no-fp-regs", - (MASK_FP|MASK_FPREGS),				\     N_("Do not use fp registers")},					\    {"alpha-as", -MASK_GAS, N_("Do not assume GAS")},			\    {"gas", MASK_GAS, N_("Assume GAS")},				\    {"ieee-conformant", MASK_IEEE_CONFORMANT,				\     N_("Request IEEE-conformant math library routines (OSF/1)")},	\    {"ieee", MASK_IEEE|MASK_IEEE_CONFORMANT,				\     N_("Emit IEEE-conformant code, without inexact exceptions")},	\    {"ieee-with-inexact", MASK_IEEE_WITH_INEXACT|MASK_IEEE_CONFORMANT,	\     N_("Emit IEEE-conformant code, with inexact exceptions")},		\    {"build-constants", MASK_BUILD_CONSTANTS,				\     N_("Do not emit complex integer constants to read-only memory")},	\    {"float-vax", MASK_FLOAT_VAX, N_("Use VAX fp")},			\    {"float-ieee", -MASK_FLOAT_VAX, N_("Do not use VAX fp")},		\    {"bwx", MASK_BWX, N_("Emit code for the byte/word ISA extension")},	\    {"no-bwx", -MASK_BWX, ""},						\    {"max", MASK_MAX,							\     N_("Emit code for the motion video ISA extension")},		\    {"no-max", -MASK_MAX, ""},						\    {"fix", MASK_FIX,							\     N_("Emit code for the fp move and sqrt ISA extension")}, 		\    {"no-fix", -MASK_FIX, ""},						\    {"cix", MASK_CIX, N_("Emit code for the counting ISA extension")},	\    {"no-cix", -MASK_CIX, ""},						\    {"explicit-relocs", MASK_EXPLICIT_RELOCS,				\     N_("Emit code using explicit relocation directives")},		\    {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, ""},			\    {"small-data", MASK_SMALL_DATA,					\     N_("Emit 16-bit relocations to the small data areas")},		\    {"large-data", -MASK_SMALL_DATA,					\     N_("Emit 32-bit relocations to the small data areas")},		\    {"tls-kernel", MASK_TLS_KERNEL,					\     N_("Emit rdval instead of rduniq for thread pointer")},		\    {"long-double-128", MASK_LONG_DOUBLE_128,				\     N_("Use 128-bit long double")},					\    {"long-double-64", -MASK_LONG_DOUBLE_128,				\     N_("Use 64-bit long double")},					\    {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT				\	 | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} }#define TARGET_DEFAULT MASK_FP|MASK_FPREGS#ifndef TARGET_CPU_DEFAULT#define TARGET_CPU_DEFAULT 0#endif#ifndef TARGET_DEFAULT_EXPLICIT_RELOCS#ifdef HAVE_AS_EXPLICIT_RELOCS#define TARGET_DEFAULT_EXPLICIT_RELOCS MASK_EXPLICIT_RELOCS#else#define TARGET_DEFAULT_EXPLICIT_RELOCS 0#endif#endifextern const char *alpha_cpu_string;	/* For -mcpu= */extern const char *alpha_tune_string;	/* For -mtune= */extern const char *alpha_fprm_string;	/* For -mfp-rounding-mode=[n|m|c|d] */extern const char *alpha_fptm_string;	/* For -mfp-trap-mode=[n|u|su|sui]  */extern const char *alpha_tp_string;	/* For -mtrap-precision=[p|f|i] */extern const char *alpha_mlat_string;	/* For -mmemory-latency= */extern const char *alpha_tls_size_string; /* For -mtls-size= */#define TARGET_OPTIONS					\{							\  {"cpu=",		&alpha_cpu_string,		\   N_("Use features of and schedule given CPU")},	\  {"tune=",		&alpha_tune_string,		\   N_("Schedule given CPU")},				\  {"fp-rounding-mode=",	&alpha_fprm_string,		\   N_("Control the generated fp rounding mode")},	\  {"fp-trap-mode=",	&alpha_fptm_string,		\   N_("Control the IEEE trap mode")},			\  {"trap-precision=",	&alpha_tp_string,		\   N_("Control the precision given to fp exceptions")},	\