/*****************************************************************************/
/*                                             COPYRIGHT (c) FREESCALE 2005  */
/*                                                                           */
/* File Name          :    $RCSfile: S12XSRAM20KV1.h,v $                     */
/*                                                                           */
/* Current Revision :      $Revision: 1.0 $                                  */
/*                                                                           */
/* PURPOSE: header file for S12X XSRAM register block                        */
/*                                                                           */
/*  ***********************************************************************  */
/*  *  THIS CODE IS ONLY INTENDED AS AN EXAMPLE OF CODE FOR THE           *  */
/*  *  METROWERKS COMPILER AND THE S12X EVB AND HAS ONLY BEEN GIVEN A     *  */
/*  *  MIMIMUM LEVEL OF TEST. IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES *  */
/*  *  AND NO PROMISE OF SUPPORT.                                         *  */
/*  ***********************************************************************  */
/*                                                                           */
/* DESCRIPTION:  Defines the XSRAM register block as a datastructure of      */
/*               type tXSRAM.                                                */
/*               This module is specific to the prototype HCS912XDP512       */
/*               0L40V silicon. Registers moved to the MMC module on         */
/*               later devices.                                              */
/*                                                                           */
/* UPDATE HISTORY                                                            */
/* REV  AUTHOR    DATE        DESCRIPTION OF CHANGE                          */
/* ---  ------    --------    ---------------------                          */
/* 1.0  r27624    25/11/03    - Initial coding                               */
/*                                                                           */
/*===========================================================================*/
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/*****************************************************************************/

#ifndef S12XSRAM20KV1_H       /*prevent duplicated includes */
#define S12XSRAM20KV1_H


#ifndef S12_COMMON_H          /*prevent duplicated includes */
#include "s12_common.h"
#endif

typedef union uXSCTRL
{
  tU08   byte;
  struct
  {
    tU08 xscavif :1;  /* XSRAM CPU Access Violation Flag */
    tU08 xsxavif :1;  /* XSRAM XGATE Access Violation Flag */
    tU08 xsavie  :1;  /* XSRAM Access Violation Interrupt Enable */
    tU08         :4;  /* not used */
    tU08 xsre    :1;  /* XSRAM Region Check Enable Bit */
  }bit;
}tXSCTRL;

#define XSCAVIF   0x01  /*bit masks */
#define XSXAVIF   0x02
#define XSAVIE 0x04
#define XSRE    0x80

typedef struct          /*XSRAM datastructure   */
{
  volatile tXSCTRL  xsctrl;  /*XSRAM control register */
  volatile tU08     xscub;   /*XSRAM code upper boundary */
  volatile tU08     xssrlb;  /*XSRAM shared lower boundary */
  volatile tU08     xssrub;  /*XSRAM shared upper boundary */
}tXSRAM;

#endif /*S12XSRAM20KV1_H */