/*****************************************************************************/
/*                                             COPYRIGHT (c) FREESCALE 2005  */
/*                                                                           */
/* File Name          :    $RCSfile: S12VREG_3V3V5.h,v $                     */
/*                                                                           */
/* Current Revision :      $Revision: 1.0 $                                  */
/*                                                                           */
/* PURPOSE: header file for S12X VREG register block                         */
/*                                                                           */
/*  ***********************************************************************  */
/*  *  THIS CODE IS ONLY INTENDED AS AN EXAMPLE OF CODE FOR THE           *  */
/*  *  METROWERKS COMPILER AND THE S12X EVB AND HAS ONLY BEEN GIVEN A     *  */
/*  *  MIMIMUM LEVEL OF TEST. IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES *  */
/*  *  AND NO PROMISE OF SUPPORT.                                         *  */
/*  ***********************************************************************  */
/*                                                                           */
/* DESCRIPTION:  Defines the VREG register block as a datastructure of       */
/*               type tVREG.                                                 */
/*                                                                           */
/* UPDATE HISTORY                                                            */
/* REV  AUTHOR      DATE        DESCRIPTION OF CHANGE                        */
/* ---  ------      --------    ---------------------                        */
/* 1.0  r54430      19/04/04    - Initial Revision                           */
/*                                                                           */
/*===========================================================================*/
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/*****************************************************************************/

#ifndef S12VREG_3V3V5_H       /*prevent duplicated includes */
#define S12VREG_3V3V5_H

#ifndef S12_COMMON_H          /*prevent duplicated includes */
#include "s12_common.h"
#endif

typedef union uVREGCTRL
{
  tU08   byte;
  struct
  {
    tU08 lvif  :1;
    tU08 lvie  :1;
    tU08 lvds  :1;
  }bit;
} tVREGCTRL;

#define LVIF   0x01  /*bit masks */
#define LVIE   0x02
#define LVDS  0x20

typedef union uVREGAPICL
{
  tU08   byte;
  struct
  {
    tU08 apif   :1;
    tU08 apie   :1;
    tU08 apife  :1;
    tU08        :4;
    tU08 apiclk :1;
  } bit;
} tVREGAPICL;

#define APIF   0x01  /*bit masks */
#define APIE   0x02
#define APIFE  0x04
#define APICLK 0x80


typedef struct {           /* vreg datastructure   */
  volatile tREG08      rsv0;     
  volatile tVREGCTRL   vregctrl;   /* Vreg Control Register */ 
  volatile tVREGAPICL  vregapicl;  /* API Control Register */  
  volatile tREG08      vregapitr;  /* API trim Register */  
  volatile tU16        vregapir;   /* API rate Register - writeable only when API disabled */
  volatile tREG08      rsv6;     
  volatile tREG08      rsv7;     
} tVREG;

#endif /*S12VREG_3V3V5_H */