---------- Begin Simulation Statistics ----------DL1.avg_blocked_cycles_no_mshrs             34.925653                       # average number of cycles each access was blockedDL1.avg_blocked_cycles_no_targets        <err: div-0>                       # average number of cycles each access was blockedDL1.avg_refs                                 1.024434                       # Average number of references to valid blocks.DL1.blocked_no_mshrs                          3845403                       # number of cycles access was blockedDL1.blocked_no_targets                              0                       # number of cycles access was blockedDL1.blocked_cycles_no_mshrs                 134303212                       # number of cycles access was blockedDL1.blocked_cycles_no_targets                       0                       # number of cycles access was blockedDL1.cache_copies                                    0                       # number of cache copies performedDL1.demand_accesses                           6918236                       # number of demand (read+write) accessesDL1.demand_avg_miss_latency               1107.446437                       # average overall miss latencyDL1.demand_avg_mshr_miss_latency          1104.446460                       # average overall mshr miss latencyDL1.demand_hits                               3500854                       # number of demand (read+write) hitsDL1.demand_miss_latency                    3784567519                       # number of demand (read+write) miss cyclesDL1.demand_miss_rate                         0.493967                       # miss rate for demand accessesDL1.demand_misses                             3417382                       # number of demand (read+write) missesDL1.demand_mshr_hits                                0                       # number of demand (read+write) MSHR hitsDL1.demand_mshr_miss_latency               3774315454                       # number of demand (read+write) MSHR miss cyclesDL1.demand_mshr_miss_rate                    0.493967                       # mshr miss rate for demand accessesDL1.demand_mshr_misses                        3417382                       # number of demand (read+write) MSHR missesDL1.fast_writes                                     0                       # number of fast writes performedDL1.mshr_cap_events                                 0                       # number of times MSHR cap was activatedDL1.no_allocate_misses                              0                       # Number of misses that were no-allocateDL1.overall_accesses                          6918236                       # number of overall (read+write) accessesDL1.overall_avg_miss_latency              1107.446437                       # average overall miss latencyDL1.overall_avg_mshr_miss_latency         1104.446460                       # average overall mshr miss latencyDL1.overall_avg_mshr_uncacheable_latency  1501.528169                       # average overall mshr uncacheable latencyDL1.overall_hits                              3500854                       # number of overall hitsDL1.overall_miss_latency                   3784567519                       # number of overall miss cyclesDL1.overall_miss_rate                        0.493967                       # miss rate for overall accessesDL1.overall_misses                            3417382                       # number of overall missesDL1.overall_mshr_hits                               0                       # number of overall MSHR hitsDL1.overall_mshr_miss_latency              3774315454                       # number of overall MSHR miss cyclesDL1.overall_mshr_miss_rate                   0.493967                       # mshr miss rate for overall accessesDL1.overall_mshr_misses                       3417382                       # number of overall MSHR missesDL1.overall_mshr_uncacheable_latency       1160663256                       # number of overall MSHR uncacheable cyclesDL1.overall_mshr_uncacheable_misses            772988                       # number of overall MSHR uncacheable missesDL1.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cacheDL1.prefetcher.num_hwpf_already_in_mshr             0                       # number of hwpf that were already in mshrDL1.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queueDL1.prefetcher.num_hwpf_evicted                     0                       # number of hwpf removed due to no buffer leftDL1.prefetcher.num_hwpf_identified                  0                       # number of hwpf identifiedDL1.prefetcher.num_hwpf_issued                      0                       # number of hwpf issuedDL1.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocatedDL1.prefetcher.num_hwpf_span_page                   0                       # number of hwpf spanning a virtual pageDL1.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation timeDL1.read_accesses                             4497616                       # number of read accesses(hits+misses)DL1.read_avg_miss_latency                 1107.991946                       # average read miss latencyDL1.read_avg_mshr_miss_latency            1104.991969                       # average read mshr miss latencyDL1.read_avg_mshr_uncacheable_latency     1478.542900                       # average read mshr uncacheable latencyDL1.read_hits                                 2275602                       # number of read hitsDL1.read_miss_latency                      2461973617                       # number of read miss cyclesDL1.read_miss_rate                           0.494043                       # miss rate for read accessesDL1.read_misses                               2222014                       # number of read missesDL1.read_mshr_miss_latency                 2455307626                       # number of read MSHR miss cyclesDL1.read_mshr_miss_rate                      0.494043                       # mshr miss rate for read accessesDL1.read_mshr_misses                          2222014                       # number of read MSHR missesDL1.read_mshr_uncacheable                      502407                       # number of read MSHR uncacheableDL1.read_mshr_uncacheable_latency           742830303                       # number of read MSHR uncacheable cyclesDL1.replacements                              3416331                       # number of replacementsDL1.sampled_refs                              3417355                       # Sample count of references to valid blocks.DL1.soft_prefetch_mshr_full                         0                       # number of mshr full events for SW prefetching instrutionsDL1.tagsinuse                             1023.827139                       # Cycle average of tags in useDL1.total_refs                                3500854                       # Total number of references to valid blocks.DL1.warmup_cycle                               100698                       # Cycle when the warmup percentage was hit.DL1.write_accesses                            2420620                       # number of write accesses(hits+misses)DL1.write_avg_miss_latency                1106.432414                       # average write miss latencyDL1.write_avg_mshr_miss_latency           1103.432439                       # average write mshr miss latencyDL1.write_avg_mshr_uncacheable_latency    1544.206552                       # average write mshr uncacheable latencyDL1.write_hits                                1225252                       # number of write hitsDL1.write_miss_latency                     1322593902                       # number of write miss cyclesDL1.write_miss_rate                          0.493827                       # miss rate for write accessesDL1.write_misses                              1195368                       # number of write missesDL1.write_mshr_miss_latency                1319007828                       # number of write MSHR miss cyclesDL1.write_mshr_miss_rate                     0.493827                       # mshr miss rate for write accessesDL1.write_mshr_misses                         1195368                       # number of write MSHR missesDL1.write_mshr_uncacheable                     270581                       # number of write MSHR uncacheableDL1.write_mshr_uncacheable_latency          417832953                       # number of write MSHR uncacheable cyclesDL1.writebacks                                1781688                       # number of writebacksL2.avg_blocked_cycles_no_mshrs              28.815069                       # average number of cycles each access was blockedL2.avg_blocked_cycles_no_targets         <err: div-0>                       # average number of cycles each access was blockedL2.avg_refs                                  0.659456                       # Average number of references to valid blocks.L2.blocked_no_mshrs                           2363282                       # number of cycles access was blockedL2.blocked_no_targets                               0                       # number of cycles access was blockedL2.blocked_cycles_no_mshrs                   68098134                       # number of cycles access was blockedL2.blocked_cycles_no_targets                        0                       # number of cycles access was blockedL2.cache_copies                                     0                       # number of cache copies performedL2.demand_accesses                            3417381                       # number of demand (read+write) accessesL2.demand_avg_miss_latency                1493.586839                       # average overall miss latencyL2.demand_avg_mshr_miss_latency           1478.491333                       # average overall mshr miss latencyL2.demand_hits                                 908765                       # number of demand (read+write) hitsL2.demand_miss_latency                     3746835842                       # number of demand (read+write) miss cyclesL2.demand_miss_rate                          0.734076                       # miss rate for demand accessesL2.demand_misses                              2508616                       # number of demand (read+write) missesL2.demand_mshr_hits                                 0                       # number of demand (read+write) MSHR hitsL2.demand_mshr_miss_latency                3708967014                       # number of demand (read+write) MSHR miss cyclesL2.demand_mshr_miss_rate                     0.734076                       # mshr miss rate for demand accessesL2.demand_mshr_misses                         2508616                       # number of demand (read+write) MSHR missesL2.fast_writes                                      0                       # number of fast writes performedL2.mshr_cap_events                                  0                       # number of times MSHR cap was activatedL2.no_allocate_misses                               0                       # Number of misses that were no-allocateL2.overall_accesses                           5199069                       # number of overall (read+write) accessesL2.overall_avg_miss_latency               1057.005427                       # average overall miss latencyL2.overall_avg_mshr_miss_latency          1478.491333                       # average overall mshr miss latencyL2.overall_avg_mshr_uncacheable_latency   1475.149464                       # average overall mshr uncacheable latencyL2.overall_hits                               1654304                       # number of overall hitsL2.overall_miss_latency                    3746835842                       # number of overall miss cyclesL2.overall_miss_rate                         0.681808                       # miss rate for overall accessesL2.overall_misses                             3544765                       # number of overall missesL2.overall_mshr_hits                                0                       # number of overall MSHR hits