cpu2.dcache.warmup_cycle                      3325149                       # Cycle when the warmup percentage was hit.cpu2.dcache.write_accesses                     479866                       # number of write accesses(hits+misses)cpu2.dcache.write_hits                         436783                       # number of write hitscpu2.dcache.write_miss_rate                  0.089781                       # miss rate for write accessescpu2.dcache.write_misses                        43083                       # number of write missescpu2.dcache.writebacks                              0                       # number of writebackscpu2.icache.avg_blocked_cycles_no_mshrs  <err: div-0>                       # average number of cycles each access was blockedcpu2.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blockedcpu2.icache.avg_refs                     48009.909375                       # Average number of references to valid blocks.cpu2.icache.blocked_no_mshrs                        0                       # number of cycles access was blockedcpu2.icache.blocked_no_targets                      0                       # number of cycles access was blockedcpu2.icache.blocked_cycles_no_mshrs                 0                       # number of cycles access was blockedcpu2.icache.blocked_cycles_no_targets               0                       # number of cycles access was blockedcpu2.icache.cache_copies                            0                       # number of cache copies performedcpu2.icache.demand_accesses                  15363491                       # number of demand (read+write) accessescpu2.icache.demand_avg_miss_latency                 0                       # average overall miss latencycpu2.icache.demand_hits                      15363171                       # number of demand (read+write) hitscpu2.icache.demand_miss_latency                     0                       # number of demand (read+write) miss cyclescpu2.icache.demand_miss_rate                 0.000021                       # miss rate for demand accessescpu2.icache.demand_misses                         320                       # number of demand (read+write) missescpu2.icache.fast_writes                             0                       # number of fast writes performedcpu2.icache.overall_accesses                 15363491                       # number of overall (read+write) accessescpu2.icache.overall_avg_miss_latency                0                       # average overall miss latencycpu2.icache.overall_hits                     15363171                       # number of overall hitscpu2.icache.overall_miss_latency                    0                       # number of overall miss cyclescpu2.icache.overall_miss_rate                0.000021                       # miss rate for overall accessescpu2.icache.overall_misses                        320                       # number of overall missescpu2.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cachecpu2.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshrcpu2.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queuecpu2.icache.prefetcher.num_hwpf_evicted             0                       # number of hwpf removed due to no buffer leftcpu2.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identifiedcpu2.icache.prefetcher.num_hwpf_issued              0                       # number of hwpf issuedcpu2.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocatedcpu2.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual pagecpu2.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation timecpu2.icache.protocol.hwpf_invalid                   0                       # hard prefetch misses to invalid blockscpu2.icache.protocol.read_invalid                 320                       # read misses to invalid blockscpu2.icache.protocol.snoop_inv_exclusive            0                       # Invalidate snoops on exclusive blockscpu2.icache.protocol.snoop_inv_invalid              0                       # Invalidate snoops on invalid blockscpu2.icache.protocol.snoop_inv_modified             0                       # Invalidate snoops on modified blockscpu2.icache.protocol.snoop_inv_owned                0                       # Invalidate snoops on owned blockscpu2.icache.protocol.snoop_inv_shared               0                       # Invalidate snoops on shared blockscpu2.icache.protocol.snoop_read_exclusive            0                       # read snoops on exclusive blockscpu2.icache.protocol.snoop_read_modified            0                       # read snoops on modified blockscpu2.icache.protocol.snoop_read_owned               0                       # read snoops on owned blockscpu2.icache.protocol.snoop_read_shared            366                       # read snoops on shared blockscpu2.icache.protocol.snoop_readex_exclusive            0                       # readEx snoops on exclusive blockscpu2.icache.protocol.snoop_readex_modified            0                       # readEx snoops on modified blockscpu2.icache.protocol.snoop_readex_owned             0                       # readEx snoops on owned blockscpu2.icache.protocol.snoop_readex_shared            0                       # readEx snoops on shared blockscpu2.icache.protocol.snoop_upgrade_owned            0                       # upgrade snoops on owned blockscpu2.icache.protocol.snoop_upgrade_shared            0                       # upgradee snoops on shared blockscpu2.icache.protocol.snoop_writeinv_exclusive            0                       # WriteInvalidate snoops on exclusive blockscpu2.icache.protocol.snoop_writeinv_invalid            0                       # WriteInvalidate snoops on invalid blockscpu2.icache.protocol.snoop_writeinv_modified            0                       # WriteInvalidate snoops on modified blockscpu2.icache.protocol.snoop_writeinv_owned            0                       # WriteInvalidate snoops on owned blockscpu2.icache.protocol.snoop_writeinv_shared            0                       # WriteInvalidate snoops on shared blockscpu2.icache.protocol.swpf_invalid                   0                       # soft prefetch misses to invalid blockscpu2.icache.protocol.write_invalid                  0                       # write misses to invalid blockscpu2.icache.protocol.write_owned                    0                       # write misses to owned blockscpu2.icache.protocol.write_shared                   0                       # write misses to shared blockscpu2.icache.read_accesses                    15363491                       # number of read accesses(hits+misses)cpu2.icache.read_hits                        15363171                       # number of read hitscpu2.icache.read_miss_rate                   0.000021                       # miss rate for read accessescpu2.icache.read_misses                           320                       # number of read missescpu2.icache.replacements                            7                       # number of replacementscpu2.icache.sampled_refs                          320                       # Sample count of references to valid blocks.cpu2.icache.tagsinuse                      258.174775                       # Cycle average of tags in usecpu2.icache.total_refs                       15363171                       # Total number of references to valid blocks.cpu2.icache.warmup_cycle                            0                       # Cycle when the warmup percentage was hit.cpu2.icache.writebacks                              0                       # number of writebackscpu2.idle_fraction                           0.017743                       # Percentage of idle cyclescpu2.not_idle_fraction                       0.982257                       # Percentage of non-idle cyclescpu2.numCycles                               15363491                       # number of cpu cycles simulatedcpu2.num_insts                               15363491                       # Number of instructions executedcpu2.num_refs                                 2566842                       # Number of memory referencescpu3.dcache.avg_blocked_cycles_no_mshrs  <err: div-0>                       # average number of cycles each access was blockedcpu3.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blockedcpu3.dcache.avg_refs                        41.053625                       # Average number of references to valid blocks.cpu3.dcache.blocked_no_mshrs                        0                       # number of cycles access was blockedcpu3.dcache.blocked_no_targets                      0                       # number of cycles access was blockedcpu3.dcache.blocked_cycles_no_mshrs                 0                       # number of cycles access was blockedcpu3.dcache.blocked_cycles_no_targets               0                       # number of cycles access was blockedcpu3.dcache.cache_copies                            0                       # number of cache copies performedcpu3.dcache.demand_accesses                   2474939                       # number of demand (read+write) accessescpu3.dcache.demand_avg_miss_latency                 0                       # average overall miss latencycpu3.dcache.demand_hits                       2413580                       # number of demand (read+write) hitscpu3.dcache.demand_miss_latency                     0                       # number of demand (read+write) miss cyclescpu3.dcache.demand_miss_rate                 0.024792                       # miss rate for demand accessescpu3.dcache.demand_misses                       61359                       # number of demand (read+write) missescpu3.dcache.fast_writes                             0                       # number of fast writes performedcpu3.dcache.overall_accesses                  2474939                       # number of overall (read+write) accessescpu3.dcache.overall_avg_miss_latency                0                       # average overall miss latencycpu3.dcache.overall_hits                      2413580                       # number of overall hitscpu3.dcache.overall_miss_latency                    0                       # number of overall miss cyclescpu3.dcache.overall_miss_rate                0.024792                       # miss rate for overall accessescpu3.dcache.overall_misses                      61359                       # number of overall missescpu3.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cachecpu3.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshrcpu3.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queuecpu3.dcache.prefetcher.num_hwpf_evicted             0                       # number of hwpf removed due to no buffer leftcpu3.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identifiedcpu3.dcache.prefetcher.num_hwpf_issued              0                       # number of hwpf issuedcpu3.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocatedcpu3.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual pagecpu3.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation timecpu3.dcache.protocol.hwpf_invalid                   0                       # hard prefetch misses to invalid blockscpu3.dcache.protocol.read_invalid               18492                       # read misses to invalid blockscpu3.dcache.protocol.snoop_inv_exclusive            0                       # Invalidate snoops on exclusive blockscpu3.dcache.protocol.snoop_inv_invalid              0                       # Invalidate snoops on invalid blockscpu3.dcache.protocol.snoop_inv_modified             0                       # Invalidate snoops on modified blockscpu3.dcache.protocol.snoop_inv_owned                0                       # Invalidate snoops on owned blockscpu3.dcache.protocol.snoop_inv_shared               0                       # Invalidate snoops on shared blockscpu3.dcache.protocol.snoop_read_exclusive            0                       # read snoops on exclusive blockscpu3.dcache.protocol.snoop_read_modified          866                       # read snoops on modified blocks