---------- Begin Simulation Statistics ----------L1.avg_blocked_cycles_no_mshrs               3.910904                       # average number of cycles each access was blockedL1.avg_blocked_cycles_no_targets         <err: div-0>                       # average number of cycles each access was blockedL1.avg_refs                                  1.004604                       # Average number of references to valid blocks.L1.blocked_no_mshrs                            205766                       # number of cycles access was blockedL1.blocked_no_targets                               0                       # number of cycles access was blockedL1.blocked_cycles_no_mshrs                     804731                       # number of cycles access was blockedL1.blocked_cycles_no_targets                        0                       # number of cycles access was blockedL1.cache_copies                                     0                       # number of cache copies performedL1.demand_accesses                            6933660                       # number of demand (read+write) accessesL1.demand_avg_miss_latency                  31.780232                       # average overall miss latencyL1.demand_avg_mshr_miss_latency             28.780242                       # average overall mshr miss latencyL1.demand_hits                                3474787                       # number of demand (read+write) hitsL1.demand_miss_latency                      109923787                       # number of demand (read+write) miss cyclesL1.demand_miss_rate                          0.498852                       # miss rate for demand accessesL1.demand_misses                              3458873                       # number of demand (read+write) missesL1.demand_mshr_hits                                 0                       # number of demand (read+write) MSHR hitsL1.demand_mshr_miss_latency                  99547201                       # number of demand (read+write) MSHR miss cyclesL1.demand_mshr_miss_rate                     0.498852                       # mshr miss rate for demand accessesL1.demand_mshr_misses                         3458873                       # number of demand (read+write) MSHR missesL1.fast_writes                                      0                       # number of fast writes performedL1.mshr_cap_events                                  0                       # number of times MSHR cap was activatedL1.no_allocate_misses                               0                       # Number of misses that were no-allocateL1.overall_accesses                           6933660                       # number of overall (read+write) accessesL1.overall_avg_miss_latency                 31.780232                       # average overall miss latencyL1.overall_avg_mshr_miss_latency            28.780242                       # average overall mshr miss latencyL1.overall_avg_mshr_uncacheable_latency   1047.978612                       # average overall mshr uncacheable latencyL1.overall_hits                               3474787                       # number of overall hitsL1.overall_miss_latency                     109923787                       # number of overall miss cyclesL1.overall_miss_rate                         0.498852                       # miss rate for overall accessesL1.overall_misses                             3458873                       # number of overall missesL1.overall_mshr_hits                                0                       # number of overall MSHR hitsL1.overall_mshr_miss_latency                 99547201                       # number of overall MSHR miss cyclesL1.overall_mshr_miss_rate                    0.498852                       # mshr miss rate for overall accessesL1.overall_mshr_misses                        3458873                       # number of overall MSHR missesL1.overall_mshr_uncacheable_latency         793174140                       # number of overall MSHR uncacheable cyclesL1.overall_mshr_uncacheable_misses             756861                       # number of overall MSHR uncacheable missesL1.prefetcher.num_hwpf_already_in_cache             0                       # number of hwpf that were already in the cacheL1.prefetcher.num_hwpf_already_in_mshr              0                       # number of hwpf that were already in mshrL1.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queueL1.prefetcher.num_hwpf_evicted                      0                       # number of hwpf removed due to no buffer leftL1.prefetcher.num_hwpf_identified                   0                       # number of hwpf identifiedL1.prefetcher.num_hwpf_issued                       0                       # number of hwpf issuedL1.prefetcher.num_hwpf_removed_MSHR_hit             0                       # number of hwpf removed because MSHR allocatedL1.prefetcher.num_hwpf_span_page                    0                       # number of hwpf spanning a virtual pageL1.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation timeL1.read_accesses                              4507508                       # number of read accesses(hits+misses)L1.read_avg_miss_latency                    31.763013                       # average read miss latencyL1.read_avg_mshr_miss_latency               28.763023                       # average read mshr miss latencyL1.read_avg_mshr_uncacheable_latency      1046.769771                       # average read mshr uncacheable latencyL1.read_hits                                  2259788                       # number of read hitsL1.read_miss_latency                         71394359                       # number of read miss cyclesL1.read_miss_rate                            0.498661                       # miss rate for read accessesL1.read_misses                                2247720                       # number of read missesL1.read_mshr_miss_latency                    64651223                       # number of read MSHR miss cyclesL1.read_mshr_miss_rate                       0.498661                       # mshr miss rate for read accessesL1.read_mshr_misses                           2247720                       # number of read MSHR missesL1.read_mshr_uncacheable                       492513                       # number of read MSHR uncacheableL1.read_mshr_uncacheable_latency            515547720                       # number of read MSHR uncacheable cyclesL1.replacements                               3457838                       # number of replacementsL1.sampled_refs                               3458862                       # Sample count of references to valid blocks.L1.soft_prefetch_mshr_full                          0                       # number of mshr full events for SW prefetching instrutionsL1.tagsinuse                              1023.477458                       # Cycle average of tags in useL1.total_refs                                 3474787                       # Total number of references to valid blocks.L1.warmup_cycle                                 66974                       # Cycle when the warmup percentage was hit.L1.write_accesses                             2426152                       # number of write accesses(hits+misses)L1.write_avg_miss_latency                   31.812189                       # average write miss latencyL1.write_avg_mshr_miss_latency              28.812196                       # average write mshr miss latencyL1.write_avg_mshr_uncacheable_latency     1050.230832                       # average write mshr uncacheable latencyL1.write_hits                                 1214999                       # number of write hitsL1.write_miss_latency                        38529428                       # number of write miss cyclesL1.write_miss_rate                           0.499207                       # miss rate for write accessesL1.write_misses                               1211153                       # number of write missesL1.write_mshr_miss_latency                   34895978                       # number of write MSHR miss cyclesL1.write_mshr_miss_rate                      0.499207                       # mshr miss rate for write accessesL1.write_mshr_misses                          1211153                       # number of write MSHR missesL1.write_mshr_uncacheable                      264348                       # number of write MSHR uncacheableL1.write_mshr_uncacheable_latency           277626420                       # number of write MSHR uncacheable cyclesL1.writebacks                                 1796123                       # number of writebacksL2.advance_pool_dist.start_dist                                # Dist. of Repl. across poolsL2.advance_pool_dist.samples                   345727                      L2.advance_pool_dist.min_value                      0                                                     0         5528    159.89%                                          1          989     28.61%                                          2          401     11.60%                                          3          202      5.84%                                          4          136      3.93%                                          5           91      2.63%                                          6           89      2.57%                                          7           93      2.69%                                          8          112      3.24%                                          9           95      2.75%                                         10         2015     58.28%                                         11         2015     58.28%                                         12         2015     58.28%                                         13         2015     58.28%                                         14         2015     58.28%                                         15       325656   9419.46%                                         16         2260     65.37%           L2.advance_pool_dist.max_value                     16                      L2.advance_pool_dist.end_distL2.avg_blocked_cycles_no_mshrs             166.220641                       # average number of cycles each access was blockedL2.avg_blocked_cycles_no_targets         <err: div-0>                       # average number of cycles each access was blockedL2.avg_refs                               1228.936330                       # Average number of references to valid blocks.L2.blocked_no_mshrs                               562                       # number of cycles access was blockedL2.blocked_no_targets                               0                       # number of cycles access was blockedL2.blocked_cycles_no_mshrs                      93416                       # number of cycles access was blockedL2.blocked_cycles_no_targets                        0                       # number of cycles access was blockedL2.cache_copies                                     0                       # number of cache copies performedL2.demand_accesses                            3458868                       # number of demand (read+write) accessesL2.demand_avg_miss_latency                 948.739995                       # average overall miss latencyL2.demand_avg_mshr_miss_latency            930.752165                       # average overall mshr miss latencyL2.demand_hits                                3454595                       # number of demand (read+write) hitsL2.demand_miss_latency                        4053966                       # number of demand (read+write) miss cyclesL2.demand_miss_rate                          0.001235                       # miss rate for demand accessesL2.demand_misses                                 4273                       # number of demand (read+write) missesL2.demand_mshr_hits                                 0                       # number of demand (read+write) MSHR hitsL2.demand_mshr_miss_latency                   3977104                       # number of demand (read+write) MSHR miss cyclesL2.demand_mshr_miss_rate                     0.001235                       # mshr miss rate for demand accessesL2.demand_mshr_misses                            4273                       # number of demand (read+write) MSHR missesL2.demote_pool_dist.start_dist                                 # Dist. of Repl. across poolsL2.demote_pool_dist.samples                    152021                      L2.demote_pool_dist.min_value                       0                                                     0       131722   8664.72%                                          1         6118    402.44%                                          2         2262    148.80%                                          3         1975    129.92%                                          4         1957    128.73%                                          5         1977    130.05%                                          6         1985    130.57%                                          7         2000    131.56%                                          8           42      2.76%                                          9            1      0.07%                                         10            1      0.07%                                         11            0      0.00%                                         12            0      0.00%                                         13            0      0.00%                                         14            0      0.00%                                         15            0      0.00%                                         16         1981    130.31%           L2.demote_pool_dist.max_value                      16                      L2.demote_pool_dist.end_distL2.fast_writes                                      0                       # number of fast writes performedL2.hash_hit                                   5250016                       # Total of hites in hash tableL2.hash_miss                                     4975                       # Total of misses in hash tableL2.hit_depth_total                            5250016                       # Total of hit depthsL2.hit_hash_depth_dist.start_dist                              # Dist. of Hash lookup depths