?? m5stats.txt
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---------- Begin Simulation Statistics ----------cpu.COM:IPB 6.578497 # Committed instructions per branchcpu.COM:IPB_0 5.986997 # Committed instructions per branchcpu.COM:IPB_1 6.177443 # Committed instructions per branchcpu.COM:IPB_2 7.872784 # Committed instructions per branchcpu.COM:IPB_3 5.952051 # Committed instructions per branchcpu.COM:IPC 4.123961 # Committed instructions per cyclecpu.COM:IPC_0 1.267507 # Committed instructions per cyclecpu.COM:IPC_1 0.446382 # Committed instructions per cyclecpu.COM:IPC_2 1.512572 # Committed instructions per cyclecpu.COM:IPC_3 0.897499 # Committed instructions per cyclecpu.COM:branches 414450 # Number of branches committedcpu.COM:branches_0 139967 # Number of branches committedcpu.COM:branches_1 47773 # Number of branches committedcpu.COM:branches_2 127020 # Number of branches committedcpu.COM:branches_3 99690 # Number of branches committedcpu.COM:bw_lim_avg 17.6299 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_0 4.1713 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_1 2.0629 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_2 7.8557 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_avg_3 3.5400 # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_events 174593 # number cycles where commit BW limit reachedcpu.COM:bw_lim_rate 4.6558 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_0 1.1016 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_1 0.5448 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_2 2.0746 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_rate_3 0.9349 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_stdev_0_mean 4.1713 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_0_stdev 6.7612 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_0_TOT 174593.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_1_mean 2.0629 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_1_stdev 7.3270 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_1_TOT 174593.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_2_mean 7.8557 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_2_stdev 16.6279 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_2_TOT 174593.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_3_mean 3.5400 # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_3_stdev 9.3431 # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_3_TOT 174593.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_limited 3078053 # number of insts not committed due to BW limitscpu.COM:bw_limited_0 728273 # number of insts not committed due to BW limitscpu.COM:bw_limited_1 360168 # number of insts not committed due to BW limitscpu.COM:bw_limited_2 1371557 # number of insts not committed due to BW limitscpu.COM:bw_limited_3 618055 # number of insts not committed due to BW limitscpu.COM:committed_per_cycle.start_dist # Number of insts commited each cyclecpu.COM:committed_per_cycle.samples 554662 cpu.COM:committed_per_cycle.min_value 0 0 1667 30.05% 1 78886 1422.24% 2 66829 1204.86% 3 60782 1095.84% 4 55126 993.87% 5 40107 723.09% 6 33758 608.62% 7 26080 470.20% 8 191427 3451.24% cpu.COM:committed_per_cycle.max_value 8 cpu.COM:committed_per_cycle.end_distcpu.COM:count 2726458 # Number of instructions committedcpu.COM:count_0 837982 # Number of instructions committedcpu.COM:count_1 295115 # Number of instructions committedcpu.COM:count_2 1000001 # Number of instructions committedcpu.COM:count_3 593360 # Number of instructions committedcpu.COM:loads 698784 # Number of loads committedcpu.COM:loads_0 250749 # Number of loads committedcpu.COM:loads_1 73254 # Number of loads committedcpu.COM:loads_2 255902 # Number of loads committedcpu.COM:loads_3 118879 # Number of loads committedcpu.COM:membars 0 # Number of memory barriers committedcpu.COM:membars_0 0 # Number of memory barriers committedcpu.COM:membars_1 0 # Number of memory barriers committedcpu.COM:membars_2 0 # Number of memory barriers committedcpu.COM:membars_3 0 # Number of memory barriers committedcpu.COM:refs 1021369 # Number of memory references committedcpu.COM:refs_0 331697 # Number of memory references committedcpu.COM:refs_1 107338 # Number of memory references committedcpu.COM:refs_2 371156 # Number of memory references committedcpu.COM:refs_3 211178 # Number of memory references committedcpu.COM:stores 322585 # Number of stores committedcpu.COM:stores_0 80948 # Number of stores committedcpu.COM:stores_1 34084 # Number of stores committedcpu.COM:stores_2 115254 # Number of stores committedcpu.COM:stores_3 92299 # Number of stores committedcpu.COM:swp_count 5995 # Number of s/w prefetches committedcpu.COM:swp_count_0 524 # Number of s/w prefetches committedcpu.COM:swp_count_1 725 # Number of s/w prefetches committedcpu.COM:swp_count_2 16 # Number of s/w prefetches committedcpu.COM:swp_count_3 4730 # Number of s/w prefetches committedcpu.DDQ:count 167468371 # cum count of instructionscpu.DDQ:count_0 50257445 # cum count of instructionscpu.DDQ:count_1 29808507 # cum count of instructionscpu.DDQ:count_2 49898955 # cum count of instructionscpu.DDQ:count_3 37503464 # cum count of instructionscpu.DDQ:rate 253 # average number of instructionscpu.DDQ:rate_0 76 # average number of instructionscpu.DDQ:rate_1 45 # average number of instructionscpu.DDQ:rate_2 75 # average number of instructionscpu.DDQ:rate_3 57 # average number of instructionscpu.DIS:chain_creation.start_dist Inst has no outstanding IDEPS 0 0.00% # Reason that chain head was created IDEP chain reached max depth 0 0.00% # Reason that chain head was created Inst is a load 0 0.00% # Reason that chain head was created Chain has multiple chained IDEPS 0 0.00% # Reason that chain head was createdcpu.DIS:chain_creation.end_distcpu.DIS:chain_head_frac 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_0 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_1 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_2 0 # fraction of insts that are chain headscpu.DIS:chain_head_frac_3 0 # fraction of insts that are chain headscpu.DIS:chain_heads 0 # number insts that are chain headscpu.DIS:chain_heads_0 0 # number insts that are chain headscpu.DIS:chain_heads_1 0 # number insts that are chain headscpu.DIS:chain_heads_2 0 # number insts that are chain headscpu.DIS:chain_heads_3 0 # number insts that are chain headscpu.DIS:chains_insuf 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_0 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_1 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_2 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_3 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_rate 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_0 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_1 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_2 0 # rate that thread had insuf chainscpu.DIS:chains_insuf_rate_3 0 # rate that thread had insuf chainscpu.DIS:count 3237103 # cumulative count of dispatched instscpu.DIS:count_0 992895 # cumulative count of dispatched instscpu.DIS:count_1 416850 # cumulative count of dispatched instscpu.DIS:count_2 1079703 # cumulative count of dispatched instscpu.DIS:count_3 747655 # cumulative count of dispatched instscpu.DIS:insufficient_chains 0 # Number of instances where dispatch stoppedcpu.DIS:mod_n_stall_avg_free no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_0 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_1 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_2 no value # avg free slots per cyclecpu.DIS:mod_n_stall_avg_free_3 no value # avg free slots per cyclecpu.DIS:mod_n_stall_frac 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_0 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_1 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_2 0 # avg stalls per cyclecpu.DIS:mod_n_stall_frac_3 0 # avg stalls per cyclecpu.DIS:mod_n_stall_free 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_0 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_1 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_2 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stall_free_3 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stalls 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_0 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_1 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_2 0 # cycles where dispatch stalled due to mod-ncpu.DIS:mod_n_stalls_3 0 # cycles where dispatch stalled due to mod-ncpu.DIS:one_rdy_insts 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_0 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_1 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_2 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_insts_3 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_ratio no value # fraction of 2-op insts w/ one ready opcpu.DIS:one_rdy_ratio_0 no value # fraction of 2-op insts w/ one ready opcpu.DIS:one_rdy_ratio_1 no value # fraction of 2-op insts w/ one ready op
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