?? m5stats.txt
字號(hào):
---------- Begin Simulation Statistics ----------cpu.COM:IPB 8.145957 # Committed instructions per branchcpu.COM:IPC 2.116709 # Committed instructions per cyclecpu.COM:branches 61381 # Number of branches committedcpu.COM:bw_lim_avg <err: div-0> # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_events 0 # number cycles where commit BW limit reachedcpu.COM:bw_lim_rate 0.0000 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_stdev_0_mean <err: div-0> # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_0_stdev <err: div-0> # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_0_TOT 0.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_limited 0 # number of insts not committed due to BW limitscpu.COM:committed_per_cycle.start_dist # Number of insts commited each cyclecpu.COM:committed_per_cycle.samples 104604 cpu.COM:committed_per_cycle.min_value 0 0 327 31.26% 1 27882 2665.48% 2 10839 1036.19% 3 5909 564.89% 4 6245 597.01% 5 2452 234.41% 6 3810 364.23% 7 2831 270.64% 8 44309 4235.88% cpu.COM:committed_per_cycle.max_value 8 cpu.COM:committed_per_cycle.end_distcpu.COM:count 500007 # Number of instructions committedcpu.COM:loads 131856 # Number of loads committedcpu.COM:membars 0 # Number of memory barriers committedcpu.COM:refs 190424 # Number of memory references committedcpu.COM:stores 58568 # Number of stores committedcpu.COM:swp_count 1669 # Number of s/w prefetches committedcpu.DDQ:count 21864839 # cum count of instructionscpu.DDQ:rate 93 # average number of instructionscpu.DIS:chain_creation.start_dist Inst has no outstanding IDEPS 0 0.00% # Reason that chain head was created IDEP chain reached max depth 0 0.00% # Reason that chain head was created Inst is a load 0 0.00% # Reason that chain head was created Chain has multiple chained IDEPS 0 0.00% # Reason that chain head was createdcpu.DIS:chain_creation.end_distcpu.DIS:chain_head_frac 0 # fraction of insts that are chain headscpu.DIS:chain_heads 0 # number insts that are chain headscpu.DIS:chains_insuf 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_rate 0 # rate that thread had insuf chainscpu.DIS:count 634630 # cumulative count of dispatched instscpu.DIS:insufficient_chains 0 # Number of instances where dispatch stoppedcpu.DIS:mod_n_stall_avg_free no value # avg free slots per cyclecpu.DIS:mod_n_stall_frac 0 # avg stalls per cyclecpu.DIS:mod_n_stall_free 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stalls 0 # cycles where dispatch stalled due to mod-ncpu.DIS:one_rdy_insts 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_ratio no value # fraction of 2-op insts w/ one ready opcpu.DIS:op_count 875841 # number of operations dispatchedcpu.DIS:op_rate 3.707750 # dispatched operations per cyclecpu.DIS:rate 2.686617 # dispatched_insts per cyclecpu.DIS:second_choice_clust 0 # Number of instructions dispatched to second-choice clustercpu.DIS:second_choice_stall 0 # Number of instructions stalled when first choice not availablecpu.DIS:serialize_stall_cycles 0 # count of cycles dispatch stalled for serializing instcpu.DIS:serializing_insts 0 # count of serializing insts dispatchedcpu.DIS:two_input_insts 0 # Number of two input instructions queuedcpu.DIS:two_input_ratio 0 # fraction of all insts having 2 inputscpu.FETCH:branch_count 87689 # Number of branches fetchedcpu.FETCH:branch_rate 0.371219 # Number of branch fetches per cyclecpu.FETCH:chance_pct 1 # Percentage of all fetch chancescpu.FETCH:chances 141201 # Number of fetch opportunitiescpu.FETCH:choice 141201 # Number of times we fetched from our first choicecpu.FETCH:count 844599 # Number of instructions fetchedcpu.FETCH:decisions 141201 # number of times the fetch stage chose between threadscpu.FETCH:idle_cycles 95018 # number of cycles where fetch stage was idlecpu.FETCH:idle_icache_blocked_cycles 0 # number of cycles where fetch was idle due to icache blockedcpu.FETCH:idle_rate 40.22 # percent of cycles fetch stage was idlecpu.FETCH:prio_changes 0 # Number of times priorities were changedcpu.FETCH:rate 3.575491 # Number of inst fetches per cyclecpu.FETCH:rate_dist.start_dist # Number of instructions fetched each cycle (Total)cpu.FETCH:rate_dist.samples 141201 cpu.FETCH:rate_dist.min_value 0 0 21 1.49% 1 6318 447.45% 2 6937 491.29% 3 11266 797.87% 4 8194 580.31% 5 13157 931.79% 6 33557 2376.54% 7 3302 233.85% 8 58449 4139.42% cpu.FETCH:rate_dist.max_value 8 cpu.FETCH:rate_dist.end_distcpu.FETCH:rate_dist_0.start_dist # Number of instructions fetched each cycle (Thread 0)cpu.FETCH:rate_dist_0.samples 141201 cpu.FETCH:rate_dist_0.min_value 0 0 21 1.49% 1 6318 447.45% 2 6937 491.29% 3 11266 797.87% 4 8194 580.31% 5 13157 931.79% 6 33557 2376.54% 7 3302 233.85% 8 58449 4139.42% cpu.FETCH:rate_dist_0.max_value 8 cpu.FETCH:rate_dist_0.end_distcpu.IFQ:count 5166561 # cumulative IFQ occupancycpu.IFQ:full_count 137254 # cumulative IFQ full countcpu.IFQ:full_rate 58.104556 # fraction of time (cycle's) IFQ was fullcpu.IFQ:latency 8.141060 # avg IFQ occupant latency (cycle's)cpu.IFQ:occupancy 21.871911 # avg IFQ occupancy (inst's)cpu.IFQ:qfull_iq_occ 1860646 # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_0.start_dist # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_0.samples 44910 cpu.IFQ:qfull_iq_occ_dist_0.min_value 0 0 9233 2055.89% 10 1211 269.65% 20 1114 248.05% 30 2172 483.63% 40 10177 2266.09% 50 14251 3173.24% 60 6752 1503.45% cpu.IFQ:qfull_iq_occ_dist_0.max_value 64 cpu.IFQ:qfull_iq_occ_dist_0.end_distcpu.IFQ:qfull_rob_occ 6023519 # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_0.start_dist # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_0.samples 44910 cpu.IFQ:qfull_rob_occ_dist_0.min_value 57 0 0 0.00% 10 0 0.00% 20 0 0.00% 30 0 0.00% 40 0 0.00% 50 74 16.48% 60 833 185.48% 70 4705 1047.65% 80 10454 2327.77% 90 5220 1162.32% 100 2104 468.49% 110 1103 245.60% 120 1576 350.92% 130 97 21.60% 140 30 6.68% 150 21 4.68% 160 34 7.57% 170 35 7.79% 180 67 14.92% 190 18557 4132.04% 200 0 0.00% cpu.IFQ:qfull_rob_occ_dist_0.max_value 196 cpu.IFQ:qfull_rob_occ_dist_0.end_distcpu.IQ:cap_events 0 # number of cycles where IQ cap was activecpu.IQ:cap_inst 0 # number of instructions held up by IQ capcpu.IQ:residence:(null).start_dist # cycles from dispatch to issuecpu.IQ:residence:(null).samples 0 cpu.IQ:residence:(null).min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0
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