?? m5stats.txt
字號:
---------- Begin Simulation Statistics ----------cpu.COM:IPB 5.995989 # Committed instructions per branchcpu.COM:IPC 1.326958 # Committed instructions per cyclecpu.COM:branches 166779 # Number of branches committedcpu.COM:bw_lim_avg <err: div-0> # Avg number not committed in cycles BW limitedcpu.COM:bw_lim_events 0 # number cycles where commit BW limit reachedcpu.COM:bw_lim_rate 0.0000 # Average number not committed due to BW (over all cycles)cpu.COM:bw_lim_stdev_0_mean <err: div-0> # standard deviation of bw_lim_avg valuecpu.COM:bw_lim_stdev_0_stdev <err: div-0> # standard deviation of bw_lim_avg value**Ignore: cpu.COM:bw_lim_stdev_0_TOT 0.0000 # standard deviation of bw_lim_avg valuecpu.COM:bw_limited 0 # number of insts not committed due to BW limitscpu.COM:committed_per_cycle.start_dist # Number of insts commited each cyclecpu.COM:committed_per_cycle.samples 228963 cpu.COM:committed_per_cycle.min_value 0 0 3902 170.42% 1 65198 2847.53% 2 28461 1243.04% 3 14358 627.09% 4 13500 589.61% 5 7355 321.23% 6 6159 269.00% 7 7906 345.30% 8 82124 3586.78% cpu.COM:committed_per_cycle.max_value 8 cpu.COM:committed_per_cycle.end_distcpu.COM:count 1000005 # Number of instructions committedcpu.COM:loads 214875 # Number of loads committedcpu.COM:membars 0 # Number of memory barriers committedcpu.COM:refs 365873 # Number of memory references committedcpu.COM:stores 150998 # Number of stores committedcpu.COM:swp_count 5252 # Number of s/w prefetches committedcpu.DDQ:count 57332887 # cum count of instructionscpu.DDQ:rate 76 # average number of instructionscpu.DIS:chain_creation.start_dist Inst has no outstanding IDEPS 0 0.00% # Reason that chain head was created IDEP chain reached max depth 0 0.00% # Reason that chain head was created Inst is a load 0 0.00% # Reason that chain head was created Chain has multiple chained IDEPS 0 0.00% # Reason that chain head was createdcpu.DIS:chain_creation.end_distcpu.DIS:chain_head_frac 0 # fraction of insts that are chain headscpu.DIS:chain_heads 0 # number insts that are chain headscpu.DIS:chains_insuf 0 # number of times thread had insuf chainscpu.DIS:chains_insuf_rate 0 # rate that thread had insuf chainscpu.DIS:count 1775191 # cumulative count of dispatched instscpu.DIS:insufficient_chains 0 # Number of instances where dispatch stoppedcpu.DIS:mod_n_stall_avg_free no value # avg free slots per cyclecpu.DIS:mod_n_stall_frac 0 # avg stalls per cyclecpu.DIS:mod_n_stall_free 0 # free slots when dispatch stalled due to mod-ncpu.DIS:mod_n_stalls 0 # cycles where dispatch stalled due to mod-ncpu.DIS:one_rdy_insts 0 # number of 2-op insts w/ one rdy opcpu.DIS:one_rdy_ratio no value # fraction of 2-op insts w/ one ready opcpu.DIS:op_count 2400027 # number of operations dispatchedcpu.DIS:op_rate 3.184720 # dispatched operations per cyclecpu.DIS:rate 2.355593 # dispatched_insts per cyclecpu.DIS:second_choice_clust 0 # Number of instructions dispatched to second-choice clustercpu.DIS:second_choice_stall 0 # Number of instructions stalled when first choice not availablecpu.DIS:serialize_stall_cycles 0 # count of cycles dispatch stalled for serializing instcpu.DIS:serializing_insts 0 # count of serializing insts dispatchedcpu.DIS:two_input_insts 0 # Number of two input instructions queuedcpu.DIS:two_input_ratio 0 # fraction of all insts having 2 inputscpu.FETCH:branch_count 415899 # Number of branches fetchedcpu.FETCH:branch_rate 0.551878 # Number of branch fetches per cyclecpu.FETCH:chance_pct 1 # Percentage of all fetch chancescpu.FETCH:chances 427547 # Number of fetch opportunitiescpu.FETCH:choice 427547 # Number of times we fetched from our first choicecpu.FETCH:count 3165141 # Number of instructions fetchedcpu.FETCH:decisions 427547 # number of times the fetch stage chose between threadscpu.FETCH:idle_cycles 326060 # number of cycles where fetch stage was idlecpu.FETCH:idle_icache_blocked_cycles 0 # number of cycles where fetch was idle due to icache blockedcpu.FETCH:idle_rate 43.27 # percent of cycles fetch stage was idlecpu.FETCH:prio_changes 0 # Number of times priorities were changedcpu.FETCH:rate 4.199989 # Number of inst fetches per cyclecpu.FETCH:rate_dist.start_dist # Number of instructions fetched each cycle (Total)cpu.FETCH:rate_dist.samples 427547 cpu.FETCH:rate_dist.min_value 0 0 491 11.48% 1 5524 129.20% 2 5246 122.70% 3 6767 158.27% 4 10680 249.80% 5 10528 246.24% 6 30467 712.60% 7 12090 282.78% 8 345754 8086.92% cpu.FETCH:rate_dist.max_value 8 cpu.FETCH:rate_dist.end_distcpu.FETCH:rate_dist_0.start_dist # Number of instructions fetched each cycle (Thread 0)cpu.FETCH:rate_dist_0.samples 427547 cpu.FETCH:rate_dist_0.min_value 0 0 491 11.48% 1 5524 129.20% 2 5246 122.70% 3 6767 158.27% 4 10680 249.80% 5 10528 246.24% 6 30467 712.60% 7 12090 282.78% 8 345754 8086.92% cpu.FETCH:rate_dist_0.max_value 8 cpu.FETCH:rate_dist_0.end_distcpu.IFQ:count 9826575 # cumulative IFQ occupancycpu.IFQ:full_count 168938 # cumulative IFQ full countcpu.IFQ:full_rate 22.417255 # fraction of time (cycle's) IFQ was fullcpu.IFQ:latency 5.535503 # avg IFQ occupant latency (cycle's)cpu.IFQ:occupancy 13.039389 # avg IFQ occupancy (inst's)cpu.IFQ:qfull_iq_occ 2907564 # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_0.start_dist # Number of insts in IQ when fetch-queue fullcpu.IFQ:qfull_iq_occ_dist_0.samples 73160 cpu.IFQ:qfull_iq_occ_dist_0.min_value 0 0 7416 1013.67% 10 4171 570.12% 20 11067 1512.71% 30 9312 1272.83% 40 19117 2613.04% 50 6958 951.07% 60 15119 2066.57% cpu.IFQ:qfull_iq_occ_dist_0.max_value 64 cpu.IFQ:qfull_iq_occ_dist_0.end_distcpu.IFQ:qfull_rob_occ 10629742 # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_0.start_dist # Number of insts in ROB when fetch-queue fullcpu.IFQ:qfull_rob_occ_dist_0.samples 73160 cpu.IFQ:qfull_rob_occ_dist_0.min_value 47 0 0 0.00% 10 0 0.00% 20 0 0.00% 30 0 0.00% 40 125 17.09% 50 494 67.52% 60 1457 199.15% 70 6971 952.84% 80 3671 501.78% 90 4480 612.36% 100 3855 526.93% 110 4738 647.62% 120 6676 912.52% 130 4921 672.64% 140 1637 223.76% 150 1375 187.94% 160 869 118.78% 170 1137 155.41% 180 406 55.49% 190 30348 4148.17% 200 0 0.00% cpu.IFQ:qfull_rob_occ_dist_0.max_value 196 cpu.IFQ:qfull_rob_occ_dist_0.end_distcpu.IQ:cap_events 0 # number of cycles where IQ cap was activecpu.IQ:cap_inst 0 # number of instructions held up by IQ capcpu.IQ:residence:(null).start_dist # cycles from dispatch to issuecpu.IQ:residence:(null).samples 0 cpu.IQ:residence:(null).min_value 0 0 0 2 0 4 0 6 0 8 0 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 30 0 32 0 34 0 36 0 38 0 40 0 42 0 44 0 46 0 48 0 50 0 52 0 54 0 56 0 58 0 60 0
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