// -*- mode:c++ -*-//Copyright (c) 2003, 2004, 2005//The Regents of The University of Michigan//All Rights Reserved//This code is part of the M5 simulator, developed by Nathan Binkert,//Erik Hallnor, Steve Raasch, and Steve Reinhardt, with contributions//from Ron Dreslinski, Dave Greene, Lisa Hsu, Kevin Lim, Ali Saidi,//and Andrew Schultz.//Permission is granted to use, copy, create derivative works and//redistribute this software and such derivative works for any purpose,//so long as the copyright notice above, this grant of permission, and//the disclaimer below appear in all copies made; and so long as the//name of The University of Michigan is not used in any advertising or//publicity pertaining to the use or distribution of this software//without specific, written prior authorization.//THIS SOFTWARE IS PROVIDED AS IS, WITHOUT REPRESENTATION FROM THE//UNIVERSITY OF MICHIGAN AS TO ITS FITNESS FOR ANY PURPOSE, AND WITHOUT//WARRANTY BY THE UNIVERSITY OF MICHIGAN OF ANY KIND, EITHER EXPRESS OR//IMPLIED, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF//MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE REGENTS OF//THE UNIVERSITY OF MICHIGAN SHALL NOT BE LIABLE FOR ANY DAMAGES,//INCLUDING DIRECT, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL//DAMAGES, WITH RESPECT TO ANY CLAIM ARISING OUT OF OR IN CONNECTION//WITH THE USE OF THE SOFTWARE, EVEN IF IT HAS BEEN OR IS HEREAFTER//ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.//////////////////////////////////////////////////////////////////////// Alpha ISA description file.////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// Output include file directives.//output header {{#include <sstream>#include <iostream>#include <iomanip>#include "config/ss_compatible_fp.hh"#include "cpu/static_inst.hh"#include "mem/mem_req.hh"  // some constructors use MemReq flags}};output decoder {{#include "base/cprintf.hh"#include "base/fenv.hh"#include "base/loader/symtab.hh"#include "config/ss_compatible_fp.hh"#include "cpu/exec_context.hh"  // for Jump::branchTarget()#include <math.h>}};output exec {{#include <math.h>#if FULL_SYSTEM#include "arch/alpha/pseudo_inst.hh"#endif#include "base/fenv.hh"#include "config/ss_compatible_fp.hh"#include "cpu/base.hh"#include "cpu/exetrace.hh"#include "sim/sim_exit.hh"}};//////////////////////////////////////////////////////////////////////// Namespace statement.  Everything below this line will be in the// AlphaISAInst namespace.//namespace AlphaISA;//////////////////////////////////////////////////////////////////////// Bitfield definitions.//// Universal (format-independent) fieldsdef bitfield OPCODE	<31:26>;def bitfield RA		<25:21>;def bitfield RB		<20:16>;// Memory formatdef signed bitfield MEMDISP <15: 0>; // displacementdef        bitfield MEMFUNC <15: 0>; // function code (same field, unsigned)// Memory-format jumpsdef bitfield JMPFUNC	<15:14>; // function code (disp<15:14>)def bitfield JMPHINT	<13: 0>; // tgt Icache idx hint (disp<13:0>)// Branch formatdef signed bitfield BRDISP <20: 0>; // displacement// Integer operate format(s>;def bitfield INTIMM	<20:13>; // integer immediate (literal)def bitfield IMM	<12:12>; // immediate flagdef bitfield INTFUNC	<11: 5>; // function codedef bitfield RC		< 4: 0>; // dest reg// Floating-point operate formatdef bitfield FA		  <25:21>;def bitfield FB		  <20:16>;def bitfield FP_FULLFUNC  <15: 5>; // complete function code    def bitfield FP_TRAPMODE  <15:13>; // trapping mode    def bitfield FP_ROUNDMODE <12:11>; // rounding mode    def bitfield FP_TYPEFUNC  <10: 5>; // type+func: handiest for decoding        def bitfield FP_SRCTYPE   <10: 9>; // source reg type        def bitfield FP_SHORTFUNC < 8: 5>; // short function code        def bitfield FP_SHORTFUNC_TOP2 <8:7>; // top 2 bits of short func codedef bitfield FC		  < 4: 0>; // dest reg// PALcode formatdef bitfield PALFUNC	<25: 0>; // function code// EV5 PAL instructions:// HW_LD/HW_STdef bitfield HW_LDST_PHYS  <15>; // address is physicaldef bitfield HW_LDST_ALT   <14>; // use ALT_MODE IPRdef bitfield HW_LDST_WRTCK <13>; // HW_LD only: fault if no write accdef bitfield HW_LDST_QUAD  <12>; // size: 0=32b, 1=64bdef bitfield HW_LDST_VPTE  <11>; // HW_LD only: is PTE fetchdef bitfield HW_LDST_LOCK  <10>; // HW_LD only: is load lockeddef bitfield HW_LDST_COND  <10>; // HW_ST only: is store conditionaldef signed bitfield HW_LDST_DISP  <9:0>; // signed displacement// HW_REIdef bitfield HW_REI_TYP <15:14>; // type: stalling vs. non-stallingkdef bitfield HW_REI_MBZ <13: 0>; // must be zero// HW_MTPR/MW_MFPRdef bitfield HW_IPR_IDX <15:0>;	 // IPR index// M5 instructionsdef bitfield M5FUNC <7:0>;def operand_types {{    'sb' : ('signed int', 8),    'ub' : ('unsigned int', 8),    'sw' : ('signed int', 16),    'uw' : ('unsigned int', 16),    'sl' : ('signed int', 32),    'ul' : ('unsigned int', 32),    'sq' : ('signed int', 64),    'uq' : ('unsigned int', 64),    'sf' : ('float', 32),    'df' : ('float', 64)}};def operands {{    # Int regs default to unsigned, but code should not count on this.    # For clarity, descriptions that depend on unsigned behavior should    # explicitly specify '.uq'.    'Ra': IntRegOperandTraits('uq', 'RA', 'IsInteger', 1),    'Rb': IntRegOperandTraits('uq', 'RB', 'IsInteger', 2),    'Rc': IntRegOperandTraits('uq', 'RC', 'IsInteger', 3),    'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),    'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),    'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),    'Mem': MemOperandTraits('uq', None,                            ('IsMemRef', 'IsLoad', 'IsStore'), 4),    'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),    'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),    'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),    # The next two are hacks for non-full-system call-pal emulation    'R0':  IntRegOperandTraits('uq', '0', None, 1),    'R16': IntRegOperandTraits('uq', '16', None, 1)}};//////////////////////////////////////////////////////////////////////// Basic instruction classes/templates/formats etc.//output header {{// uncomment the following to get SimpleScalar-compatible disassembly// (useful for diffing output traces).// #define SS_COMPATIBLE_DISASSEMBLY    /**     * Base class for all Alpha static instructions.     */    class AlphaStaticInst : public StaticInst<AlphaISA>    {      protected:	/// Make AlphaISA register dependence tags directly visible in	/// this class and derived classes.  Maybe these should really	/// live here and not in the AlphaISA namespace.	enum DependenceTags {	    FP_Base_DepTag = AlphaISA::FP_Base_DepTag,	    Fpcr_DepTag = AlphaISA::Fpcr_DepTag,	    Uniq_DepTag = AlphaISA::Uniq_DepTag,	    IPR_Base_DepTag = AlphaISA::IPR_Base_DepTag	};	/// Constructor.	AlphaStaticInst(const char *mnem, MachInst _machInst,			OpClass __opClass)	    : StaticInst<AlphaISA>(mnem, _machInst, __opClass)	{	}	/// Print a register name for disassembly given the unique	/// dependence tag number (FP or int).	void printReg(std::ostream &os, int reg) const;	std::string	generateDisassembly(Addr pc, const SymbolTable *symtab) const;    };}};output decoder {{    void    AlphaStaticInst::printReg(std::ostream &os, int reg) const    {	if (reg < FP_Base_DepTag) {	    ccprintf(os, "r%d", reg);	}	else {	    ccprintf(os, "f%d", reg - FP_Base_DepTag);	}    }    std::string    AlphaStaticInst::generateDisassembly(Addr pc,					 const SymbolTable *symtab) const    {	std::stringstream ss;	ccprintf(ss, "%-10s ", mnemonic);	// just print the first two source regs... if there's	// a third one, it's a read-modify-write dest (Rc),	// e.g. for CMOVxx	if (_numSrcRegs > 0) {	    printReg(ss, _srcRegIdx[0]);	}	if (_numSrcRegs > 1) {	    ss << ",";	    printReg(ss, _srcRegIdx[1]);	}	// just print the first dest... if there's a second one,	// it's generally implicit	if (_numDestRegs > 0) {	    if (_numSrcRegs > 0)		ss << ",";	    printReg(ss, _destRegIdx[0]);	}	return ss.str();    }}};// Declarations for execute() methods.def template BasicExecDeclare {{    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;}};// Basic instruction class declaration template.def template BasicDeclare {{    /**     * Static instruction class for "%(mnemonic)s".     */    class %(class_name)s : public %(base_class)s    {      public:	/// Constructor.	%(class_name)s(MachInst machInst);	%(BasicExecDeclare)s    };}};// Basic instruction class constructor template.def template BasicConstructor {{    inline %(class_name)s::%(class_name)s(MachInst machInst)	 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)    {	%(constructor)s;    }}};// Basic instruction class execute method template.def template BasicExecute {{    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,				  Trace::InstRecord *traceData) const    {	Fault fault = No_Fault;	%(fp_enable_check)s;	%(op_decl)s;	%(op_rd)s;	%(code)s;	if (fault == No_Fault) {	    %(op_wb)s;	}	return fault;    }}};// Basic decode template.def template BasicDecode {{    return new %(class_name)s(machInst);}};// Basic decode template, passing mnemonic in as string arg to constructor.def template BasicDecodeWithMnemonic {{    return new %(class_name)s("%(mnemonic)s", machInst);}};// The most basic instruction format... used only for a few misc. instsdef format BasicOperate(code, *flags) {{    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code), flags)    header_output = BasicDeclare.subst(iop)    decoder_output = BasicConstructor.subst(iop)    decode_block = BasicDecode.subst(iop)    exec_output = BasicExecute.subst(iop)}};//////////////////////////////////////////////////////////////////////// Nop//output header {{    /**     * Static instruction class for no-ops.  This is a leaf class.     */    class Nop : public AlphaStaticInst    {	/// Disassembly of original instruction.	const std::string originalDisassembly;      public:	/// Constructor	Nop(const std::string _originalDisassembly, MachInst _machInst)	    : AlphaStaticInst("nop", _machInst, No_OpClass),	      originalDisassembly(_originalDisassembly)	{	    flags[IsNop] = true;	}	~Nop() { }	std::string	generateDisassembly(Addr pc, const SymbolTable *symtab) const;	%(BasicExecDeclare)s    };}};output decoder {{    std::string Nop::generateDisassembly(Addr pc,					 const SymbolTable *symtab) const    {#ifdef SS_COMPATIBLE_DISASSEMBLY	return originalDisassembly;#else	return csprintf("%-10s (%s)", "nop", originalDisassembly);#endif    }    /// Helper function for decoding nops.  Substitute Nop object    /// for original inst passed in as arg (and delete latter).    inline    AlphaStaticInst *    makeNop(AlphaStaticInst *inst)    {	AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);	delete inst;	return nop;    }}};output exec {{    Fault    Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const    {	return No_Fault;    }}};// integer & FP operate instructions use Rc as dest, so check for// Rc == 31 to detect nopsdef template OperateNopCheckDecode {{ {     AlphaStaticInst *i = new %(class_name)s(machInst);     if (RC == 31) {         i = makeNop(i);     }     return i; }}};// Like BasicOperate format, but generates NOP if RC/FC == 31def format BasicOperateWithNopCheck(code, *opt_args) {{    iop = InstObjParams(name, Name, 'AlphaStaticInst', CodeBlock(code),			opt_args)    header_output = BasicDeclare.subst(iop)    decoder_output = BasicConstructor.subst(iop)    decode_block = OperateNopCheckDecode.subst(iop)    exec_output = BasicExecute.subst(iop)}};//////////////////////////////////////////////////////////////////////// Integer operate instructions//output header {{    /**     * Base class for integer immediate instructions.     */    class IntegerImm : public AlphaStaticInst    {      protected:	/// Immediate operand value (unsigned 8-bit int).	uint8_t imm;	/// Constructor	IntegerImm(const char *mnem, MachInst _machInst, OpClass __opClass)	    : AlphaStaticInst(mnem, _machInst, __opClass), imm(INTIMM)	{	}	std::string	generateDisassembly(Addr pc, const SymbolTable *symtab) const;    };}};output decoder {{    std::string    IntegerImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const    {	std::stringstream ss;	ccprintf(ss, "%-10s ", mnemonic);	// just print the first source reg... if there's	// a second one, it's a read-modify-write dest (Rc),	// e.g. for CMOVxx	if (_numSrcRegs > 0) {	    printReg(ss, _srcRegIdx[0]);	    ss << ",";	}