ss << (int)imm; 	if (_numDestRegs > 0) {	    ss << ",";	    printReg(ss, _destRegIdx[0]);	}	return ss.str();    }}};def template RegOrImmDecode {{ {     AlphaStaticInst *i =         (IMM) ? (AlphaStaticInst *)new %(class_name)sImm(machInst)               : (AlphaStaticInst *)new %(class_name)s(machInst);     if (RC == 31) {         i = makeNop(i);     }     return i; }}};// Primary format for integer operate instructions:// - Generates both reg-reg and reg-imm versions if Rb_or_imm is used.// - Generates NOP if RC == 31.def format IntegerOperate(code, *opt_flags) {{    # If the code block contains 'Rb_or_imm', we define two instructions,    # one using 'Rb' and one using 'imm', and have the decoder select    # the right one.    uses_imm = (code.find('Rb_or_imm') != -1)    if uses_imm:	orig_code = code        # base code is reg version:        # rewrite by substituting 'Rb' for 'Rb_or_imm'	code = re.sub(r'Rb_or_imm', 'Rb', orig_code)        # generate immediate version by substituting 'imm'        # note that imm takes no extenstion, so we extend        # the regexp to replace any extension as well        imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)    # generate declaration for register version    cblk = CodeBlock(code)    iop = InstObjParams(name, Name, 'AlphaStaticInst', cblk, opt_flags)    header_output = BasicDeclare.subst(iop)    decoder_output = BasicConstructor.subst(iop)    exec_output = BasicExecute.subst(iop)    if uses_imm:        # append declaration for imm version        imm_cblk = CodeBlock(imm_code)        imm_iop = InstObjParams(name, Name + 'Imm', 'IntegerImm', imm_cblk,				opt_flags)	header_output += BasicDeclare.subst(imm_iop)        decoder_output += BasicConstructor.subst(imm_iop)        exec_output += BasicExecute.subst(imm_iop)        # decode checks IMM bit to pick correct version	decode_block = RegOrImmDecode.subst(iop)    else:        # no imm version: just check for nop        decode_block = OperateNopCheckDecode.subst(iop)}};//////////////////////////////////////////////////////////////////////// Floating-point instructions////	Note that many FP-type instructions which do not support all the//	various rounding & trapping modes use the simpler format//	BasicOperateWithNopCheck.//output exec {{    /// Check "FP enabled" machine status bit.  Called when executing any FP    /// instruction in full-system mode.    /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault    /// if not.  Non-full-system mode: always returns No_Fault.#if FULL_SYSTEM    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)    {	Fault fault = No_Fault;	// dummy... this ipr access should not fault	if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {	    fault = Fen_Fault;	}	return fault;    }#else    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)    {	return No_Fault;    }#endif}};output header {{    /**     * Base class for general floating-point instructions.  Includes     * support for various Alpha rounding and trapping modes.  Only FP     * instructions that require this support are derived from this     * class; the rest derive directly from AlphaStaticInst.     */    class AlphaFP : public AlphaStaticInst    {      public:	/// Alpha FP rounding modes.	enum RoundingMode {	    Chopped = 0,	///< round toward zero	    Minus_Infinity = 1, ///< round toward minus infinity	    Normal = 2,		///< round to nearest (default)	    Dynamic = 3,	///< use FPCR setting (in instruction)	    Plus_Infinity = 3	///< round to plus inifinity (in FPCR)	};	/// Alpha FP trapping modes.	/// For instructions that produce integer results, the	/// "Underflow Enable" modes really mean "Overflow Enable", and	/// the assembly modifier is V rather than U.	enum TrappingMode {	    /// default: nothing enabled	    Imprecise = 0,		   ///< no modifier	    /// underflow/overflow traps enabled, inexact disabled	    Underflow_Imprecise = 1,	   ///< /U or /V	    Underflow_Precise = 5,	   ///< /SU or /SV	    /// underflow/overflow and inexact traps enabled	    Underflow_Inexact_Precise = 7  ///< /SUI or /SVI	};      protected:	/// Map Alpha rounding mode to C99 constants from <fenv.h>.	static const int alphaToC99RoundingMode[];	/// Map enum RoundingMode values to disassembly suffixes.	static const char *roundingModeSuffix[];	/// Map enum TrappingMode values to FP disassembly suffixes.	static const char *fpTrappingModeSuffix[];	/// Map enum TrappingMode values to integer disassembly suffixes.	static const char *intTrappingModeSuffix[];	/// This instruction's rounding mode.	RoundingMode roundingMode;	/// This instruction's trapping mode.	TrappingMode trappingMode;	/// Have we warned about this instruction's unsupported	/// rounding mode (if applicable)?	mutable bool warnedOnRounding;	/// Have we warned about this instruction's unsupported	/// trapping mode (if applicable)?	mutable bool warnedOnTrapping;	/// Constructor	AlphaFP(const char *mnem, MachInst _machInst, OpClass __opClass)	    : AlphaStaticInst(mnem, _machInst, __opClass),	      roundingMode((enum RoundingMode)FP_ROUNDMODE),	      trappingMode((enum TrappingMode)FP_TRAPMODE),	      warnedOnRounding(false),	      warnedOnTrapping(false)	{	}	int getC99RoundingMode(uint64_t fpcr_val) const;	// This differs from the AlphaStaticInst version only in	// printing suffixes for non-default rounding & trapping modes.	std::string	generateDisassembly(Addr pc, const SymbolTable *symtab) const;    };}};output decoder {{    int    AlphaFP::getC99RoundingMode(uint64_t fpcr_val) const    {	if (roundingMode == Dynamic) {	    return alphaToC99RoundingMode[bits(fpcr_val, 59, 58)];	}	else {	    return alphaToC99RoundingMode[roundingMode];	}    }    std::string    AlphaFP::generateDisassembly(Addr pc, const SymbolTable *symtab) const    {	std::string mnem_str(mnemonic);#ifndef SS_COMPATIBLE_DISASSEMBLY	std::string suffix("");	suffix += ((_destRegIdx[0] >= FP_Base_DepTag)		   ? fpTrappingModeSuffix[trappingMode]		   : intTrappingModeSuffix[trappingMode]);	suffix += roundingModeSuffix[roundingMode];	if (suffix != "") {	    mnem_str = csprintf("%s/%s", mnemonic, suffix);	}#endif	std::stringstream ss;	ccprintf(ss, "%-10s ", mnem_str.c_str());	// just print the first two source regs... if there's	// a third one, it's a read-modify-write dest (Rc),	// e.g. for CMOVxx	if (_numSrcRegs > 0) {	    printReg(ss, _srcRegIdx[0]);	}	if (_numSrcRegs > 1) {	    ss << ",";	    printReg(ss, _srcRegIdx[1]);	}	// just print the first dest... if there's a second one,	// it's generally implicit	if (_numDestRegs > 0) {	    if (_numSrcRegs > 0)		ss << ",";	    printReg(ss, _destRegIdx[0]);	}	return ss.str();    }    const int AlphaFP::alphaToC99RoundingMode[] = {	FE_TOWARDZERO,	// Chopped	FE_DOWNWARD,	// Minus_Infinity	FE_TONEAREST,	// Normal	FE_UPWARD	// Dynamic in inst, Plus_Infinity in FPCR    };    const char *AlphaFP::roundingModeSuffix[] = { "c", "m", "", "d" };    // mark invalid trapping modes, but don't fail on them, because    // you could decode anything on a misspeculated path    const char *AlphaFP::fpTrappingModeSuffix[] =	{ "", "u", "INVTM2", "INVTM3", "INVTM4", "su", "INVTM6", "sui" };    const char *AlphaFP::intTrappingModeSuffix[] =	{ "", "v", "INVTM2", "INVTM3", "INVTM4", "sv", "INVTM6", "svi" };}};// FP instruction class execute method template.  Handles non-standard// rounding modes.def template FloatingPointExecute {{    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,				  Trace::InstRecord *traceData) const    {	if (trappingMode != Imprecise) {	    warn("%s: non-standard trapping mode not supported",		 generateDisassembly(0, NULL));	    warnedOnTrapping = true;	}	Fault fault = No_Fault;	%(fp_enable_check)s;	%(op_decl)s;	%(op_rd)s;#if USE_FENV	if (roundingMode == Normal) {	    %(code)s;	} else {	    fesetround(getC99RoundingMode(xc->readFpcr()));	    %(code)s;	    fesetround(FE_TONEAREST);	}#else	if (roundingMode != Normal && !warnedOnRounding) {	    warn("%s: non-standard rounding mode not supported",		 generateDisassembly(0, NULL));	    warnedOnRounding = true;	}	%(code)s;#endif	if (fault == No_Fault) {	    %(op_wb)s;	}	return fault;    }}};// FP instruction class execute method template where no dynamic// rounding mode control is needed.  Like BasicExecute, but includes// check & warning for non-standard trapping mode.def template FPFixedRoundingExecute {{    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,				  Trace::InstRecord *traceData) const    {	if (trappingMode != Imprecise) {	    warn("%s: non-standard trapping mode not supported",		 generateDisassembly(0, NULL));	    warnedOnTrapping = true;	}	Fault fault = No_Fault;	%(fp_enable_check)s;	%(op_decl)s;	%(op_rd)s;	%(code)s;	if (fault == No_Fault) {	    %(op_wb)s;	}	return fault;    }}};def template FloatingPointDecode {{ {     AlphaStaticInst *i = new %(class_name)s(machInst);     if (FC == 31) {	 i = makeNop(i);     }     return i; }}};// General format for floating-point operate instructions:// - Checks trapping and rounding mode flags.  Trapping modes//   currently unimplemented (will fail).// - Generates NOP if FC == 31.def format FloatingPointOperate(code, *opt_args) {{    iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)    decode_block = FloatingPointDecode.subst(iop)    header_output = BasicDeclare.subst(iop)    decoder_output = BasicConstructor.subst(iop)    exec_output = FloatingPointExecute.subst(iop)}};// Special format for cvttq where rounding mode is pre-decodeddef format FPFixedRounding(code, class_suffix, *opt_args) {{    Name += class_suffix    iop = InstObjParams(name, Name, 'AlphaFP', CodeBlock(code), opt_args)    decode_block = FloatingPointDecode.subst(iop)    header_output = BasicDeclare.subst(iop)    decoder_output = BasicConstructor.subst(iop)    exec_output = FPFixedRoundingExecute.subst(iop)}};//////////////////////////////////////////////////////////////////////// Memory-format instructions: LoadAddress, Load, Store//output header {{    /**     * Base class for general Alpha memory-format instructions.     */    class Memory : public AlphaStaticInst    {      protected:	/// Memory request flags.  See mem_req_base.hh.        unsigned memAccessFlags;	/// Pointer to EAComp object.	const StaticInstPtr<AlphaISA> eaCompPtr;	/// Pointer to MemAcc object.	const StaticInstPtr<AlphaISA> memAccPtr;	/// Constructor	Memory(const char *mnem, MachInst _machInst, OpClass __opClass,	       StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,	       StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)	    : AlphaStaticInst(mnem, _machInst, __opClass),	      memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)	{	}	std::string	generateDisassembly(Addr pc, const SymbolTable *symtab) const;      public:	const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }	const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }    };    /**     * Base class for memory-format instructions using a 32-bit     * displacement (i.e. most of them).     */    class MemoryDisp32 : public Memory    {      protected:	/// Displacement for EA calculation (signed).	int32_t disp;	/// Constructor.	MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,		     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,		     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)	    : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),	      disp(MEMDISP)	{	}    };    /**     * Base class for a few miscellaneous memory-format insts     * that don't interpret the disp field: wh64, fetch, fetch_m, ecb.     * None of these instructions has a destination register either.     */    class MemoryNoDisp : public Memory    {      protected:	/// Constructor	MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,		     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,		     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)	    : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)	{	}	std::string	generateDisassembly(Addr pc, const SymbolTable *symtab) const;    };}};output decoder {{    std::string    Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const    {	return csprintf("%-10s %c%d,%d(r%d)", mnemonic,			flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);    }    std::string    MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const    {	return csprintf("%-10s (r%d)", mnemonic, RB);    }}};def format LoadAddress(code) {{    iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))    header_output = BasicDeclare.subst(iop)    decoder_output = BasicConstructor.subst(iop)    decode_block = BasicDecode.subst(iop)    exec_output = BasicExecute.subst(iop)}};def template LoadStoreDeclare {{    /**     * Static instruction class for "%(mnemonic)s".     */    class %(class_name)s : public %(base_class)s    {      protected:	/**	 * "Fake" effective address computation class for "%(mnemonic)s".	 */	class EAComp : public %(base_class)s	{