/* decode and dispatch new operations */    /* ==> insert ops w/ no deps or all regs ready --> reg deps resolved */    dispatch();    decodeQueue->tick();    start_decode();    fetch();    //==================================================================    //    //  End-Of-Cycle    //    //==================================================================    //    //  Do every-cycle statistics here    //    //  We do them here because the machine is in a consistent state    //  at this point (unlike prior to this)    //    for (int i = 0; i < numIQueues; ++i)	IQ[i]->tick_stats();    LSQ->tick_stats();    decodeQueue->tick_stats();    currentROBCount = ROB.num_active();    for (int i = 0; i < number_of_threads; ++i) {	// update buffer occupancy stats	IFQ_count += ifq[i].num_total();	IFQ_fcount[i] += ((ifq[i].num_total() == ifq_size) ? 1 : 0);	if (!thread_info[i].active)	    continue;	ROB_count[i] += ROB.num_thread(i);	ROB_occ_dist[i].sample(ROB.num_thread(i));	//  Update register occ stats	reg_int_thrd_occ[i] += used_int_physical_regs[i];	reg_fp_thrd_occ[i] += used_fp_physical_regs[i];    }#if DEBUG_CAUSES    if (floss_this_cycle <= 0)	ccprintf(cerr, "Didn't FLOSS this cycle! (%n)\n\n", curTick);#endif    if (!tickEvent.scheduled())	tickEvent.schedule(curTick + cycles(1));}BranchPred *FullCPU::getBranchPred(){    return branch_pred;}BEGIN_DECLARE_SIM_OBJECT_PARAMS(FullCPU)    Param<int> num_threads;    Param<int> clock;#if FULL_SYSTEM    SimObjectParam<AlphaITB *> itb;    SimObjectParam<AlphaDTB *> dtb;    SimObjectParam<FunctionalMemory *> mem;    SimObjectParam<System *> system;    Param<int> cpu_id;    Param<bool> interval_stats;#else    SimObjectVectorParam<Process *> workload;#endif // FULL_SYSTEM    Param<Counter> max_insts_any_thread;    Param<Counter> max_insts_all_threads;    Param<Counter> max_loads_any_thread;    Param<Counter> max_loads_all_threads;    SimObjectParam<BaseCache *> icache;    SimObjectParam<BaseCache *> dcache;    SimpleEnumParam<FullCPU::SoftwarePrefetchPolicy> sw_prefetch_policy;    SimObjectVectorParam<BaseIQ *> iq;    Param<int> rob_size;    Param<int> lsq_size;    Param<int> storebuffer_size;    Param<int> fetch_width;    Param<int> lines_to_fetch;    Param<int> num_icache_ports;    Param<int> fetch_branches;    Param<int> ifq_size;    Param<int> decode_to_dispatch;    SimObjectParam<BranchPred *> branch_pred;    SimpleEnumParam<FetchPolicyEnum> fetch_policy;    Param<bool> fetch_pri_enable;    VectorParam<unsigned> icount_bias;    Param<bool> mt_frontend;    Param<int> decode_width;    Param<int> dispatch_to_issue;    VectorParam<unsigned> rob_caps;    SimpleEnumParam<FullCPU::DispatchPolicyEnum> dispatch_policy;    Param<bool> loose_mod_n_policy;    Param<bool> use_hm_predictor;    Param<bool> use_lr_predictor;    Param<bool> use_lat_predictor;    Param<unsigned> max_chains;    Param<unsigned> max_wires;    SimpleEnumParam<ChainWireInfo::MappingPolicy> chain_wire_policy;    Param<int> issue_width;    VectorParam<unsigned> issue_bandwidth;    Param<bool> inorder_issue;    SimpleEnumParam<FullCPU::MemDisambiguationEnum> disambig_mode;    Param<bool> prioritized_issue;    SimObjectVectorParam<FuncUnitPool *> fupools;    VectorParam<unsigned> thread_weights;    Param<int> mispred_recover;    Param<int> fault_handler_delay;    Param<unsigned> iq_comm_latency;    Param<int> commit_width;    Param<bool> prioritized_commit;    SimpleEnumParam<FullCPU::CommitModelEnum> commit_model;    Param<int> pc_sample_interval;    Param<bool> function_trace;    Param<Tick> function_trace_start;    SimObjectParam<PipeTrace *> ptrace;    Param<int> width;    Param<bool> defer_registration;END_DECLARE_SIM_OBJECT_PARAMS(FullCPU)static const char *fetch_policy_strings[] = {    "RR", "IC", "ICRC", "Ideal", "Conf",    "Redundant", "RedIC", "RedSlack", "Rand"};static const char *commit_model_strings[] = {    "smt", "perthread", "sscalar", "rr"};const char *dispatch_policy_strings[] = {    "mod_n", "perqueue", "dependence"};static const char *sw_prefetch_policy_strings[] = {    "enable", "disable", "squash"};static const char *disambig_mode_strings[] = {    "conservative", "normal", "oracle"};static const char *chainWirePolicyStrings[] = {    "OneToOne", "Static", "StaticStall", "Dynamic"};BEGIN_INIT_SIM_OBJECT_PARAMS(FullCPU)    INIT_PARAM(num_threads,	       "number of HW thread contexts (dflt = # of processes)"),    INIT_PARAM(clock, "clock speed"),#if FULL_SYSTEM    INIT_PARAM(itb, "Instruction TLB"),    INIT_PARAM(dtb, "Data TLB"),    INIT_PARAM(mem, "memory"),    INIT_PARAM(system, "system object"),    INIT_PARAM(cpu_id, "processor ID"),    INIT_PARAM_DFLT(interval_stats, "Turn on interval stats for this cpu",		    false),#else    INIT_PARAM(workload, "processes to run"),#endif // FULL_SYSTEM    INIT_PARAM_DFLT(max_insts_any_thread,		    "terminate when any thread reaches this inst count",		    0),    INIT_PARAM_DFLT(max_insts_all_threads,		    "terminate when all threads have reached this inst count",		    0),    INIT_PARAM_DFLT(max_loads_any_thread,		    "terminate when any thread reaches this load count",		    0),    INIT_PARAM_DFLT(max_loads_all_threads,		    "terminate when all threads have reached this load count",		    0),    INIT_PARAM(icache, "L1 instruction cache object"),    INIT_PARAM(dcache, "L1 data cache object"),    INIT_ENUM_PARAM_DFLT(sw_prefetch_policy,		    "software prefetch policy",		    sw_prefetch_policy_strings, FullCPU::SWP_ENABLE),    INIT_PARAM(iq, "instruction queue object"),    INIT_PARAM(rob_size, "reorder buffer size"),    INIT_PARAM(lsq_size, "load/store queue size"),    INIT_PARAM(storebuffer_size, "store buffer size"),    INIT_PARAM(fetch_width, "instruction fetch BW (insts/cycle)"),    // Give a large default so this doesn't play into choking fetch.    INIT_PARAM_DFLT(lines_to_fetch, "instruction fetch BW (lines/cycle)", 999),    INIT_PARAM(num_icache_ports, "number of icache ports"),    INIT_PARAM(fetch_branches, "stop fetching after 'n'-th branch"),    INIT_PARAM(ifq_size, "instruction fetch queue size (in insts)"),    INIT_PARAM(decode_to_dispatch, "decode to dispatch latency (cycles)"),    INIT_PARAM(branch_pred, "branch predictor object"),    INIT_ENUM_PARAM_DFLT(fetch_policy, "SMT fetch policy",			 fetch_policy_strings, IC),    INIT_PARAM_DFLT(fetch_pri_enable, "use thread priorities in fetch", false),    INIT_PARAM(icount_bias, "per-thread static icount bias"),    INIT_PARAM_DFLT(mt_frontend, "use the multi-threaded IFQ and FTDQ", true),    INIT_PARAM(decode_width, "instruction decode BW (insts/cycle)"),    INIT_PARAM_DFLT(dispatch_to_issue,		    "minimum dispatch to issue latency (cycles)", 1),    INIT_PARAM(rob_caps, "maximum per-thread ROB occupancy"),    INIT_ENUM_PARAM_DFLT(dispatch_policy,			 "method for selecting destination IQ",			 dispatch_policy_strings, FullCPU::MODULO_N),    INIT_PARAM_DFLT(loose_mod_n_policy, "loosen the Mod-N dispatch policy",		    true),    INIT_PARAM_DFLT(use_hm_predictor,  "enable hit/miss predictor", false),    INIT_PARAM_DFLT(use_lr_predictor,  "enable left/right predictor", true),    INIT_PARAM_DFLT(use_lat_predictor, "enable latency predictor", false),    INIT_PARAM_DFLT(max_chains, "maximum number of dependence chains", 64),    INIT_PARAM_DFLT(max_wires, "maximum number of dependence chain wires", 64),    INIT_ENUM_PARAM_DFLT(chain_wire_policy,			 "chain-wire assignment policy",			 chainWirePolicyStrings, ChainWireInfo::OneToOne),    INIT_PARAM(issue_width, "instruction issue B/W (insts/cycle)"),    INIT_PARAM(issue_bandwidth, "maximum per-thread issue rate"),    INIT_PARAM_DFLT(inorder_issue, "issue instruction inorder", false),    INIT_ENUM_PARAM_DFLT(disambig_mode,		    "memory address disambiguation mode",		    disambig_mode_strings, FullCPU::DISAMBIG_NORMAL),    INIT_PARAM_DFLT(prioritized_issue, "issue HP thread first", false),    INIT_PARAM(fupools, "list of FU pools"),    INIT_PARAM(thread_weights, "issue priority weights"),    INIT_PARAM(mispred_recover, "branch misprediction recovery latency"),    INIT_PARAM_DFLT(fault_handler_delay,		    "latency from commit of faulting inst to fetch of handler",		    5),    INIT_PARAM_DFLT(iq_comm_latency,	       "writeback communication latency (cycles) for multiple IQ's",1),    INIT_PARAM(commit_width, "instruction commit BW (insts/cycle)"),    INIT_PARAM_DFLT(prioritized_commit, "use thread priorities in commit",		    false),    INIT_ENUM_PARAM_DFLT(commit_model, "commit model", commit_model_strings,			 FullCPU::COMMIT_MODEL_SMT),    INIT_PARAM(pc_sample_interval, "PC sample interval"),    INIT_PARAM_DFLT(function_trace, "Enable function trace", false),    INIT_PARAM_DFLT(function_trace_start, "Cycle to start function trace", 0),    INIT_PARAM(ptrace, "pipeline tracing object"),    INIT_PARAM(width, "default machine width"),    INIT_PARAM_DFLT(defer_registration, "defer registration with system "		    "(for sampling)", false)END_INIT_SIM_OBJECT_PARAMS(FullCPU)CREATE_SIM_OBJECT(FullCPU){#if FULL_SYSTEM    // full-system only supports a single thread for the moment    int actual_num_threads = 1;#else    // in non-full-system mode, we infer the number of threads from    // the workload if it's not explicitly specified    int actual_num_threads =	num_threads != 0 ? num_threads : workload.size();    if (workload.size() == 0) {	fatal("Must specify at least one workload!");    }#endif    FullCPU::Params *params = new FullCPU::Params();    params->name = getInstanceName();    params->numberOfThreads = actual_num_threads;    params->max_insts_any_thread = max_insts_any_thread;    params->max_insts_all_threads = max_insts_all_threads;    params->max_loads_any_thread = max_loads_any_thread;    params->max_loads_all_threads = max_loads_all_threads;    params->deferRegistration = defer_registration;    params->clock = clock;    params->functionTrace = function_trace;    params->functionTraceStart = function_trace_start;#if FULL_SYSTEM    params->system = system;    params->cpu_id = cpu_id;#endif    //    //  Issue bandwidth caps    //    vector<unsigned> ibw(SMT_MAX_THREADS);    unsigned issue_bandwidth_size = 0;    if (issue_bandwidth.isValid())	issue_bandwidth_size = issue_bandwidth.size();    if (issue_bandwidth_size >= SMT_MAX_THREADS) {	// copy what we need...	for (int i = 0; i < SMT_MAX_THREADS; ++i)	    ibw[i] = issue_bandwidth[i];    }    else {	for (int i = 0; i < SMT_MAX_THREADS; ++i) {	    if (i < issue_bandwidth_size)		ibw[i] = issue_bandwidth[i];	    else		ibw[i] = issue_width;	}    }    //    //  ROB caps    //    vector<unsigned> rc(SMT_MAX_THREADS);    unsigned rob_caps_size = 0;    if (rob_caps.isValid())	rob_caps_size = rob_caps.size();    if (rob_caps_size >= SMT_MAX_THREADS) {	// copy what we need...	for (int i = 0; i < SMT_MAX_THREADS; ++i)	    rc[i] = (rob_caps[i]==0) ? rob_size : rob_caps[i];    } else {	for (int i = 0; i < SMT_MAX_THREADS; ++i) {	    if (i < rob_caps_size)		rc[i] = (rob_caps[i]==0) ? rob_size : rob_caps[i];	    else		rc[i] = rob_size;	}    }    //    //  I-Count biasing    //    vector<unsigned> _ic_bias(SMT_MAX_THREADS);    unsigned icount_bias_size = 0;    if (icount_bias.isValid())	icount_bias_size = icount_bias.size();    if (icount_bias_size >= SMT_MAX_THREADS) {	// copy what we need...	for (int i = 0; i < SMT_MAX_THREADS; ++i)	    _ic_bias[i] = icount_bias[i];    } else {	for (int i = 0; i < SMT_MAX_THREADS; ++i) {	    if (i < icount_bias_size)		_ic_bias[i] = icount_bias[i];	    else		_ic_bias[i] = 0;	}    }    //    //  Issue BW weighting    //    vector<unsigned> tweights(SMT_MAX_THREADS);    unsigned thread_weights_size = 0;    if (thread_weights.isValid())	thread_weights_size = thread_weights.size();    if (thread_weights_size >= SMT_MAX_THREADS) {	// copy what we need...	for (int i = 0; i < SMT_MAX_THREADS; ++i)	    tweights[i] = thread_weights[i];    }    else {	for (int i = 0; i < SMT_MAX_THREADS; ++i) {	    if (i < thread_weights_size)		tweights[i] = thread_weights[i];	    else		tweights[i] = 1;	}    }    //  can't do prioritized issue if thread weights aren't specified    bool pi = prioritized_issue;    if (pi && !thread_weights.isValid()) {	cerr << "Warning: prioritized_issue selected, but thread_wieghts not "	    "specified\n         --> Turning prioritized_issue OFF\n\n";	pi = false;    }    FullCPU *cpu = new FullCPU(params,#if FULL_SYSTEM		      itb, dtb, mem,#else		      workload,#endif // FULL_SYSTEM		      icache->getInterface(),		      dcache->getInterface(),		      sw_prefetch_policy,		      iq,		      rob_size,		      lsq_size,		      storebuffer_size,		      fetch_width,		      lines_to_fetch,		      num_icache_ports,		      fetch_branches,		      ifq_size,		      decode_to_dispatch,		      branch_pred,		      fetch_policy,		      fetch_pri_enable,		      _ic_bias,		      mt_frontend,		      decode_width,		      dispatch_to_issue,		      rc,		      dispatch_policy,		      loose_mod_n_policy,		      use_hm_predictor,		      use_lr_predictor,		      use_lat_predictor,		      max_chains,		      max_wires,		      chain_wire_policy,		      issue_width,		      ibw,		      inorder_issue,		      disambig_mode,		      pi,		      fupools,		      tweights,		      mispred_recover,		      fault_handler_delay,		      iq_comm_latency,		      commit_width,		      prioritized_commit,		      commit_model,		      pc_sample_interval,		      (PipeTrace *)ptrace);    return cpu;}REGISTER_SIM_OBJECT("FullCPU", FullCPU)