?? dctslow.vhd
字號:
USE ieee.std_logic_arith.all;
LIBRARY std ;
USE std.textio.all;
ENTITY dctslowcontroller IS
PORT(
clk : IN std_logic ;
dctselect : IN std_logic ;
mode : IN std_logic_vector (1 downto 0) ;
reset : IN std_logic ;
ck : OUT std_logic ;
clk_1 : OUT std_logic ;
columns : OUT std_logic_vector (2 downto 0) ;
enable_0 : OUT std_logic ;
enable_1 : OUT std_logic ;
enable_2 : OUT std_logic ;
enable_and12 : OUT std_logic ;
next_in : OUT std_logic ;
read : OUT std_logic ;
rows : OUT std_logic_vector (2 downto 0) ;
rst : OUT std_logic ;
clk_0 : BUFFER std_logic ;
clk_2 : BUFFER std_logic ;
compl : BUFFER std_logic ;
enable_div : BUFFER std_logic ;
first : BUFFER std_logic
);
-- Declarations
END dctslowcontroller ;
--
--
ARCHITECTURE beh3 OF dctslowcontroller IS
signal next_in_tmp,enable_clk_0,enable_clk_2,clk_2_tmp : std_logic;
signal enable_and12_tmp,enable_div_tmp,enable_ck,first_tmp : std_logic;
signal read_tmp,read_tmp2 : std_logic;
signal address,address_tmp,add_tmp2 : std_logic_vector(5 downto 0);
BEGIN
with dctselect select
rows <= add_tmp2(5 downto 3) when '1',
add_tmp2(2 downto 0) when others;
with dctselect select
columns <= add_tmp2(2 downto 0) when '1',
add_tmp2(5 downto 3) when others;
clk_0 <= clk and enable_clk_0;
clk_1 <= clk_0;
ck <= clk and enable_ck;
rst <= reset;
enable_0 <= not reset;
enable_1 <= not reset;
enable_2 <= not reset;
next_in <= next_in_tmp and first_tmp;
main : process(clk)
variable cyccount : integer range 0 to 63 := 0;
variable state : integer range 0 to 12 := 0;
variable counter : integer range 0 to 11 := 0;
begin
address_tmp <= conv_std_logic_vector(cyccount,6);
if rising_edge(clk) then
if clk_2 = '1' then
if counter = 7 then
read_tmp <= '1';
counter := 0;
else
counter := counter + 1;
read_tmp <= '0';
end if;
end if;
if (reset = '1')then
first_tmp <= '1';
cyccount := 0;
counter := 0;
state := 0;
address <= "000000";
compl <= '0';
enable_div_tmp <= '1';
next_in_tmp <= '0';
enable_clk_0 <= '0';
enable_clk_2 <= '0';
enable_ck <= '0';
enable_and12_tmp <= '0';
read_tmp <= '0';
read_tmp2 <= '0';
read <= '0';
clk_2_tmp <= '0';
clk_2 <= '0';
else
clk_2 <= clk_2_tmp;
address <= address_tmp;
compl <= next_in_tmp;
enable_div_tmp <= not compl;
clk_2_tmp <= (not enable_div_tmp) and enable_clk_2;
enable_and12_tmp <= '1';
enable_and12 <= enable_and12_tmp;
enable_div <= enable_div_tmp;
add_tmp2 <= address;
first <= first_tmp;
read_tmp2 <= read_tmp;
read <= read_tmp2;
case state is
when 0 =>
first_tmp <= '1';
cyccount := 0;
next_in_tmp <= '1';
state := 1;
when 1 =>
next_in_tmp <= '0';
enable_ck <= '1';
state := 2;
when 2 =>
if counter = 0 then
enable_and12_tmp <= '0';
else
enable_and12_tmp <= '1';
end if;
state := 3;
when 3 =>
state := 4;
enable_clk_0 <= '1';
when 4 =>
state := 5;
enable_clk_2 <= '1';
when 5 =>
if mode = "00" then
state := 6;
elsif mode = "01" then
state := 12;
elsif mode = "10" then
state := 11;
else
state := 9;
end if;
when 9 =>
state := 10;
when 10 =>
state := 11;
when 11 =>
state := 12;
when 12 =>
state := 6;
when 6 =>
state := 7;
when 7 =>
state := 8;
when 8 =>
if cyccount = 7 then
first_tmp <= '0';
cyccount := cyccount + 1;
elsif cyccount = 63 then
first_tmp <= '1';
cyccount := 0;
else
cyccount := cyccount + 1;
end if;
next_in_tmp <= '1';
state := 1;
end case;
end if;
end if;
end process main;
END beh3;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY DCT8_slow IS
PORT(
clk : IN std_logic ;
dctselect : IN std_logic ;
din : IN std_logic ;
mode : IN std_logic_vector (1 downto 0) ;
reset : IN std_logic ;
doutput : OUT std_logic_vector (15 DOWNTO 0) ;
next_in : OUT std_logic ;
read : OUT std_logic
);
-- Declarations
END DCT8_slow ;
--
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
LIBRARY std ;
USE std.textio.ALL;
LIBRARY work;
ARCHITECTURE struct OF DCT8_slow IS
-- Architecture declarations
-- Internal signal declarations
SIGNAL ck : std_logic;
SIGNAL clk_0 : std_logic;
SIGNAL clk_1 : std_logic;
SIGNAL clk_2 : std_logic;
SIGNAL columns : std_logic_vector(2 downto 0);
SIGNAL compl : std_logic;
SIGNAL enable_0 : std_logic;
SIGNAL enable_1 : std_logic;
SIGNAL enable_2 : std_logic;
SIGNAL enable_and12 : std_logic;
SIGNAL enable_div : std_logic;
SIGNAL enable_rom : std_logic;
SIGNAL first : std_logic;
SIGNAL inadd_1_1 : std_logic_vector(11 downto 0);
SIGNAL inadd_1_2 : std_logic_vector(11 downto 0);
SIGNAL inadd_2_1 : std_logic_vector(15 downto 0);
SIGNAL inadd_2_2 : std_logic_vector(15 downto 0);
SIGNAL outadd_1 : std_logic_vector(12 downto 0);
SIGNAL outadd_2 : std_logic_vector(15 downto 0);
SIGNAL outdct : std_logic_vector(15 downto 0);
SIGNAL register_1 : std_logic_vector(12 DOWNTO 0);
SIGNAL rom_output : std_logic_vector(11 DOWNTO 0);
SIGNAL rows : std_logic_vector(2 downto 0);
SIGNAL rst : std_logic;
-- Component Declarations
COMPONENT ROM64
PORT (
columns : IN std_logic_vector (2 downto 0);
compl : IN std_logic ;
enable_rom : IN std_logic ;
rows : IN std_logic_vector (2 downto 0);
output : OUT std_logic_vector (11 DOWNTO 0)
);
END COMPONENT;
COMPONENT add12slow
PORT (
a : IN std_logic_vector (11 downto 0);
b : IN std_logic_vector (11 downto 0);
output : OUT std_logic_vector (12 downto 0)
);
END COMPONENT;
COMPONENT add16bits
PORT (
a : IN std_logic_vector (15 downto 0);
b : IN std_logic_vector (15 downto 0);
output : OUT std_logic_vector (15 downto 0)
);
END COMPONENT;
COMPONENT and15
PORT (
enable : IN std_logic ;
input : IN std_logic_vector (15 downto 0);
output : OUT std_logic_vector (15 downto 0)
);
END COMPONENT;
COMPONENT cyclereg
PORT (
ck : IN std_logic ;
din : IN std_logic ;
first : IN std_logic ;
mode : IN std_logic_vector (1 downto 0);
rst : IN std_logic ;
enable_rom : OUT std_logic
);
END COMPONENT;
COMPONENT dctslowcontroller
PORT (
clk : IN std_logic ;
dctselect : IN std_logic ;
mode : IN std_logic_vector (1 downto 0);
reset : IN std_logic ;
ck : OUT std_logic ;
clk_1 : OUT std_logic ;
columns : OUT std_logic_vector (2 downto 0);
enable_0 : OUT std_logic ;
enable_1 : OUT std_logic ;
enable_2 : OUT std_logic ;
enable_and12 : OUT std_logic ;
next_in : OUT std_logic ;
read : OUT std_logic ;
rows : OUT std_logic_vector (2 downto 0);
rst : OUT std_logic ;
clk_0 : BUFFER std_logic ;
clk_2 : BUFFER std_logic ;
compl : BUFFER std_logic ;
enable_div : BUFFER std_logic ;
first : BUFFER std_logic
);
END COMPONENT;
COMPONENT div2_9_en
PORT (
ain : IN std_logic_vector (12 downto 0);
enable : IN std_logic ;
aout : OUT std_logic_vector (11 downto 0)
);
END COMPONENT;
COMPONENT reg12bits
PORT (
ain : IN std_logic_vector (11 downto 0);
clk : IN std_logic ;
enable : IN std_logic ;
aout : OUT std_logic_vector (11 downto 0)
);
END COMPONENT;
COMPONENT reg13bits
PORT (
ain : IN std_logic_vector (12 downto 0);
clk : IN std_logic ;
enable : IN std_logic ;
aout : OUT std_logic_vector (12 downto 0)
);
END COMPONENT;
COMPONENT reg16bits
PORT (
ain : IN std_logic_vector (15 downto 0);
clk : IN std_logic ;
enable : IN std_logic ;
aout : OUT std_logic_vector (15 downto 0)
);
END COMPONENT;
-- Optional embedded configurations
--synopsys translate_off
FOR ALL : ROM64 USE ENTITY work.ROM64;
FOR ALL : add12slow USE ENTITY work.add12slow;
FOR ALL : add16bits USE ENTITY work.add16bits;
FOR ALL : and15 USE ENTITY work.and15;
FOR ALL : cyclereg USE ENTITY work.cyclereg;
FOR ALL : dctslowcontroller USE ENTITY work.dctslowcontroller;
FOR ALL : div2_9_en USE ENTITY work.div2_9_en;
FOR ALL : reg12bits USE ENTITY work.reg12bits;
FOR ALL : reg13bits USE ENTITY work.reg13bits;
FOR ALL : reg16bits USE ENTITY work.reg16bits;
--synopsys translate_on
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 1 eb1
inadd_2_1 <= register_1(12)®ister_1(12)®ister_1(12)®ister_1;
-- HDL Embedded Text Block 2 eb2
--with dctselect select
-- doutput <= outdct(9 downto 2) when '1',
-- outdct(7 downto 0) when others;
-- 14 downto 0 is the useful output
doutput <= outdct;
-- Instance port mappings.
I10 : ROM64
PORT MAP (
columns => columns,
compl => compl,
enable_rom => enable_rom,
rows => rows,
output => rom_output
);
I2 : add12slow
PORT MAP (
a => inadd_1_1,
b => inadd_1_2,
output => outadd_1
);
I4 : add16bits
PORT MAP (
a => inadd_2_1,
b => inadd_2_2,
output => outadd_2
);
I6 : and15
PORT MAP (
enable => enable_and12,
input => outdct,
output => inadd_2_2
);
I8 : cyclereg
PORT MAP (
ck => ck,
din => din,
first => first,
mode => mode,
rst => rst,
enable_rom => enable_rom
);
I1 : dctslowcontroller
PORT MAP (
clk => clk,
dctselect => dctselect,
mode => mode,
reset => reset,
ck => ck,
clk_1 => clk_1,
columns => columns,
enable_0 => enable_0,
enable_1 => enable_1,
enable_2 => enable_2,
enable_and12 => enable_and12,
next_in => next_in,
read => read,
rows => rows,
rst => rst,
clk_0 => clk_0,
clk_2 => clk_2,
compl => compl,
enable_div => enable_div,
first => first
);
I5 : div2_9_en
PORT MAP (
ain => register_1,
enable => enable_div,
aout => inadd_1_2
);
I0 : reg12bits
PORT MAP (
ain => rom_output,
clk => clk_0,
enable => enable_0,
aout => inadd_1_1
);
I7 : reg13bits
PORT MAP (
ain => outadd_1,
clk => clk_1,
enable => enable_1,
aout => register_1
);
I9 : reg16bits
PORT MAP (
ain => outadd_2,
clk => clk_2,
enable => enable_2,
aout => outdct
);
END struct;?? 快捷鍵說明
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