module NewRLCCtrl(Clock, Reset, Start, Enable, Done, Over, Countgey, Run16, ZeroCoeff, LoadData, RSTCount, IncrCount, MuxSel,
                LoadMuxOut, LoadPDC, LoadZC, IncrZC, RSTZC, RSTPDC, sDC, sAC, sZRL, sEOB, sEOB2, sDone, LoadCoeffOut, RSTZCO);

input Clock, Reset, Start, Enable, Done, Over, Countgey, Run16, ZeroCoeff;
output LoadData, RSTCount, IncrCount, MuxSel,
       LoadMuxOut, LoadPDC, LoadZC, IncrZC, RSTZC, RSTPDC, sDC, sAC, sZRL, sEOB, sEOB2, LoadCoeffOut, RSTZCO, sDone;

reg LoadData, RSTCount, IncrCount, MuxSel,
    LoadMuxOut, LoadPDC, LoadZC, IncrZC, RSTZC, RSTPDC, sDC, sAC, sZRL, sEOB, sEOB2, sDone,  LoadCoeffOut, RSTZCO;

reg [1:0] CurrState, NextState;
parameter [1:0] ST0 = 2'b00, ST1 = 2'b01, ST2 = 2'b10, ST3 = 2'b11;
parameter DC = 1'b0, AC = 1'b1;

always@(posedge Clock or posedge Reset)
  begin
  if(Reset)
    CurrState = ST0;
  else
    CurrState = NextState;
  end

always@(CurrState or Start or Enable or Done or Over or Countgey or Run16 or ZeroCoeff)
  begin:FSM_COMB
  LoadData=0; 
  RSTCount=0; 
  IncrCount=0; 
  MuxSel=0;
  LoadMuxOut=0; 
  LoadPDC=0;
  LoadZC=0;   
  IncrZC=0; 
  RSTZC=0; 
  RSTPDC=0;
  sDC=0; 
  sAC=0; 
  sZRL=0; 
  sEOB=0; 
  LoadCoeffOut=0;
  RSTZCO = 0;
	sDone = 0;
  sEOB2 = 0;
  
  case(CurrState)
    ST0:  if(Start & Enable)
            begin
            LoadData = 1;
            NextState = ST1;
            end
          else
            begin
            RSTCount = 1;
            RSTZC = 1;
            RSTPDC = 1;
            NextState = ST0;
            end

    ST1:  if(Enable)
    				begin
          	LoadData = 1;
          	LoadPDC = 1;
          	MuxSel = DC;
          	LoadMuxOut = 1;
          	NextState = ST2;
          	end
          else
          	NextState = ST1;

    ST2:  if(Enable)
		    		begin
          	LoadData = 1;
          	MuxSel = AC;
          	LoadMuxOut = 1;
          	LoadCoeffOut = 1;
						RSTZCO = 1;
          	sDC = 1;
          	IncrCount = 1;
          	NextState = ST3;
          	end
          else
          	NextState = ST2;

    ST3:  if(Enable)
		    		begin
          	LoadData = 1;
          	MuxSel = AC;
          	LoadMuxOut = 1;
          	LoadCoeffOut = 1;
          	IncrCount = 1;
						if(Done)
		   				sDone = 1;          
          	if(ZeroCoeff)
            	begin
            	if(Countgey)
              	begin
              	sEOB = 1;
              	sEOB2 = 1;
              	RSTZC = 1;
	           		RSTZCO = 1;	
              	if(Over)
                	NextState = ST0;
              	else
                	begin
                 	LoadPDC = 1;
                 	MuxSel = DC;		     				 
                 	NextState = ST2;
                 	end //end else 
              	end  //end if(Countgey)
            	else
              	begin
              	IncrZC = 1;
						  	LoadZC = 1;
              	if(Run16)
                	sZRL = 1;
              	NextState = ST3;
              	end //end else
            	end // end if(ZeroCoeff)
          	else	 
            	begin
            	RSTZC = 1;
            	LoadZC = 1;            
            	sAC = 1;
            	if(Countgey)
              	begin 
              	sEOB2 = 1;
              	if(Over)
              		NextState = ST0;
              	else
              		begin		     			
		     					LoadPDC = 1;
                	MuxSel = DC;
									NextState = ST2; 
                	end //end else                 		 
		  					end //end if(Countgey)
            	else
              	NextState = ST3;
            	end //end else
          	end //end if(Enable)
          else
          	NextState = ST3;
          	
    default: NextState = ST0;
    endcase
	end

endmodule