Zero Runlength Encoder

The zero-runlength coder is the first stage of the entropy encoder.  It has a three stage pipeline.  The first stage contains logic for calculating delta DC, the second stage is where the runlength count is extracted and the third stage decrements the outgoing -ve coefficients. The control logic also generates the appropriate status bit telling what kind of coefficient is being output.

The significance of each status bit is as follows:

 - The DC bit, if set indicates that the coefficient being output is the DC value and thus requires different treatment     than the other 63 AC values.

 - The AC bit indicates that that the coefficient output is a non-zero AC coefficient and the associated zero count     indicates the preceding zeros.

 - The ZRL bit indictates that a bunch of 16 zeros were counted,

 - EOB bit indictates thr end-of-block with a zero-value.

 - The BlkEnd (block end) bit is mandatory indicating the 64th value of block.
 
These status bits are propagated through the pipeline and used by later stages to take the necessary actions. 

The zero runlength encoder is implemented as a FSM controller and a corresponding architecture.