/*******************************************************************/
/*	This module implements the strip logic stage		       */
/*	of the Entropy encoder 				 	             */
/*******************************************************************/

module Stripper(	Coefficient, 
                	Runlength, 
                	Category, 
                	DC, 
                	AC, 
                	EOB, 
                	ZRL,
                	EOB20, 
                	Flush, 
                	Clk, 
                	Reset, 
                	Enable,
                	CoefficientOut, 
                	RunlengthOut, 
                	CategoryOut, 
                	DCOut, 
                	ACOut, 
                	EOBOut, 
                	ZRLOut,
                	EOB2Out, 
                	LoadControl
);

//              MODULE INPUTS
input [10:0] 	Coefficient;	// Coefficient input
input [3:0] 	Runlength; 		// Runlength input
input [3:0]	Category;		// Category input
input 		DC; 			// 4-bit status field input
input 		AC; 
input 		EOB; 
input 		ZRL; 
input 		EOB20; 		// BlkEnd input
input 		Clk; 			// Clock signal input
input 		Flush; 		// Pipeline flush signal
input 		Reset; 		// low asserted system-wide reset
input 		Enable;		// System-wide enable signal

//             MODULE OUTPUTS
output [10:0] 	CoefficientOut; // Coefficient output
output [3:0] 	       RunlengthOut;   // Runlength output 	 
output [3:0]	       CategoryOut;	  // Category output
output 		DCOut;          // DC status bit output
output 		ACOut;          // AC status bit output
output 		EOBOut;         // EOB condition bit output
output 		ZRLOut;         // 16 zeros count status output
output 		EOB2Out;        // BLKEND status bit output 
output 		LoadControl;	// Controls loading of data into 
						// the strip logic stages 

reg [10:0] 		CoefficientOut;
reg [3:0] 		RunlengthOut;  
reg [3:0] 		CategoryOut;
reg 			DCOut; 
reg 			ACOut;
reg 			EOBOut; 
reg 			ZRLOut; 
reg 			EOB2Out;
wire 			LoadControl;	

//              INTERNAL REGISTERS
reg [10:0]		Coefficient1; 	// The registers making up the 
reg [10:0]		Coefficient2; 	// the stages of the strip logic
reg [10:0]		Coefficient3;        // refer to article
reg [10:0]		Coefficient4;

reg [3:0]		Runlength1; 
reg [3:0]		Runlength2; 
reg [3:0]		Runlength3; 
reg [3:0]		Runlength4;

reg [3:0]		Category1; 
reg [3:0]		Category2; 
reg [3:0]		Category3; 
reg [3:0]		Category4;
 
reg 			DC1;
reg 			DC2; 
reg 			DC3;
reg 			DC4; 

reg			AC1; 
reg 			AC2; 
reg			AC3;
reg 			AC4;

reg 			EOB1;
reg 			EOB2; 
reg			EOB3; 
reg			EOB4; 

reg			ZRL1;
reg 			ZRL2;
reg 			ZRL3; 
reg 			ZRL4;

reg 			EOB21; 
reg 			EOB22; 
reg 			EOB23; 
reg			EOB24;

// The LoadControl signal is generated if any of the 4 status signals 
// are received.  Also the external controller generates the Flush  
// signal to empty the pipeline after the previous stages have   
// stopped receiving new data.  Since the LoadControl is not  
// generated for zero coefficients, the strip action is accomplished

or or1(LoadControl, DC, AC, EOB, ZRL, Flush);

always @(posedge Clk or negedge Reset)
begin
      if(!Reset)
    		begin
    		DC1 <= 0;
    		AC1 <= 0;
    		ZRL1 <= 0;
    		EOB1 <= 0;
		EOB21 <= 0;
		
    		DC2 <= 0;
    		AC2 <= 0;
    		ZRL2 <= 0;
    		EOB2 <= 0;
		EOB22 <= 0;
		
    		DC3 <= 0;
    		AC3 <= 0;
    		ZRL3 <= 0;
    		EOB3 <= 0;
		EOB23 <= 0;
		
    		DC4 <= 0;
    		AC4 <= 0;
    		ZRL4 <= 0;
    		EOB4 <= 0;
		EOB24 <= 0;
		
    		DCOut <= 0;
    		ACOut <= 0;
    		ZRLOut <= 0;
    		EOBOut <= 0;
    		EOB2Out <= 0;	
    		end
  	else if(LoadControl & Enable)
      	begin
        	DC1 <= DC;
        	AC1 <= AC;
        	EOB1 <= EOB;        
        	ZRL1 <= ZRL;
        	EOB21 <= EOB20;
        
        	DC2 <= DC1;
        	AC2 <= AC1;
        	EOB2 <= EOB1;        
        	ZRL2 <= ZRL1;
        	EOB22 <= EOB21;
        
        	DC3 <= DC2;
        	AC3 <= AC2;
        	EOB3 <= EOB2;        
        	ZRL3 <= ZRL2;
        	EOB23 <= EOB22;
                
        	DC4 <= DC3;
        	AC4 <= AC3;
        	EOB4 <= EOB3;        
        	ZRL4 <= ZRL3;
        	EOB24 <= EOB23;
        
        	DCOut <= DC4;
        	ACOut <= AC4;
        	EOBOut <= EOB4;        
        	EOB2Out <= EOB24;
    
// The signal ZRLout is conditionally output depending on the 
// presense of EOB in the previous stages of strip logic
    
        	if (ZRL4 & ZRL3 & ZRL2 & EOB1)
          		ZRLOut <= 0;
        	else if(ZRL3 & ZRL4 & EOB2)
          		ZRLOut <= 0;
        	else if(ZRL4 & EOB3)
          		ZRLOut <= 0;
        	else
          		ZRLOut <= ZRL4;

        	Coefficient1 <= Coefficient;
        	Runlength1 <= Runlength;
        	Category1 <= Category;
        
        	Coefficient2 <= Coefficient1;
        	Runlength2 <= Runlength1;
        	Category2 <= Category1;
         
        	Coefficient3 <= Coefficient2;
        	Runlength3 <= Runlength2;
        	Category3 <= Category2;

        	Coefficient4 <= Coefficient3;
        	Runlength4 <= Runlength3;
        	Category4 <= Category3;

        	CoefficientOut <= Coefficient4;
        	RunlengthOut <= Runlength4;
        	CategoryOut <= Category4;
    		end
end
endmodule