?? mcu.h

?? ZIGBEE 2006協議棧 BAT測試代碼 RADIO PULSE MG2455
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#define	xFCN_ADR1		XBYTE[0x2702]
#define	xFCN_ADR0		XBYTE[0x2703]
#define	xFCN_DAT3		XBYTE[0x2704]
#define	xFCN_DAT2		XBYTE[0x2705]
#define	xFCN_DAT1		XBYTE[0x2706]
#define	xFCN_DAT0		XBYTE[0x2707]
#define	xFCN_LEN1		XBYTE[0x2708]
#define	xFCN_LEN0		XBYTE[0x2709]
#define	xFCN_CPT1		XBYTE[0x270A]
#define	xFCN_CPT0		XBYTE[0x270B]
#define	xFCN_STS1		XBYTE[0x270C]
#define	xFCN_STS0		XBYTE[0x270D]
#define	xFCN_NOWAIT	XBYTE[0x270E]
//----------------------------------------------------
// FCNTL TEST Patterns
//----------------------------------------------------
#define	xFCN_T0DAT3	XBYTE[0x2710]
#define	xFCN_T0DAT2	XBYTE[0x2711]
#define	xFCN_T0DAT1	XBYTE[0x2712]
#define	xFCN_T0DAT0	XBYTE[0x2713]
#define	xFCN_T1DAT3	XBYTE[0x2714]
#define	xFCN_T1DAT2	XBYTE[0x2715]
#define	xFCN_T1DAT1	XBYTE[0x2716]
#define	xFCN_T1DAT0	XBYTE[0x2717]
//----------------------------------------------------
// FCNTL Timing Parameters
//----------------------------------------------------
#define	xFCN_TERS1		XBYTE[0x2720]
#define	xFCN_TERS0		XBYTE[0x2721]
#define	xFCN_TME1		XBYTE[0x2722]
#define	xFCN_TME0		XBYTE[0x2723]
#define	xFCN_TPRG		XBYTE[0x2724]
#define	xFCN_TRCV		XBYTE[0x2725]
#define	xFCN_THV1		XBYTE[0x2726]
#define	xFCN_THV0		XBYTE[0x2727]
#define	xFCN_TNVS		XBYTE[0x2728]  
#define	xFCN_TNVH		XBYTE[0x2729]
#define	xFCN_TPGS		XBYTE[0x272A]
#define	xFCN_TNVH1		XBYTE[0x272B]
//----------------------------------------------------
// CODEC Control
//----------------------------------------------------
#define	xENCMUT1		XBYTE[0x2740]
#define	xENCMUT0		XBYTE[0x2741]
#define	xENCPCM1		XBYTE[0x2742]
#define	xENCPCM0		XBYTE[0x2743]
#define	xENCCDC		XBYTE[0x2744]
#define	xENCCTL		XBYTE[0x2745]
//------------------------
// ENCCTL
//------------------------
// [7:6]	: -
// [5]	: B16
// [4] 	: MUT
// [3:2]	: 0=PCM, 1=ULAW, 2=ALAW, 3=ADPCM
// [1] 	: Initialize
// [0]	: Enable
//------------------------
#define	x2746			XBYTE[0x2746]
#define	x2747			XBYTE[0x2747]
#define	xDECMUT1		XBYTE[0x2748]
#define	xDECMUT0		XBYTE[0x2749]
#define	xDECPCM1		XBYTE[0x274A]
#define	xDECPCM0		XBYTE[0x274B]
#define	xDECCDC		XBYTE[0x274C]
#define	xDECCTL		XBYTE[0x274D]
//------------------------
// DECCTL
//------------------------
// [7]	: LBP(Codec Loopback)
// [6]	: -
// [5]	: B16
// [4] 	: MUT
// [3:2]	: 0=PCM, 1=ULAW, 2=ALAW, 3=ADPCM
// [1] 	: Initialize
// [0]	: Enable
//------------------------
//----------------------------------------------------
// VOICE TX FIFO Control (From I2S to MAC TX FIFO)
//----------------------------------------------------
#define 	xVTF_DAT		XBYTE[0x2750]
#define 	xVTF_MUT		XBYTE[0x2751]
#define 	xVTF_CTL		XBYTE[0x2752]
//------------------------
// VTFCTL
//------------------------
// [7:4]	: -
// [3]	: DMA Enable(VTxFIFO --> MTxFIFO)
// [2]	: MUTE
// [1] 	: Clear Write/Read Pointer
// [0]	: Initialize VTXFIFO[] to Mute Data
//------------------------
#define 	xVTF_RP		XBYTE[0x2753]
#define 	xVTF_WP		XBYTE[0x2754]
#define 	xVTF_SIZE		XBYTE[0x2755]
#define 	xVTF_HTHR		XBYTE[0x2756]
#define 	xVTF_LTHR		XBYTE[0x2757]
#define 	xVTF_ROOM		XBYTE[0x2758]
#define 	xVTF_2759		XBYTE[0x2759]
#define 	xVTF_STS		XBYTE[0x275A]
#define 	xVTD_SIZE		XBYTE[0x275B]
#define 	xNEVOS			XBYTE[0x275C]
#define 	xNEVNGT1		XBYTE[0x275D]
#define 	xNEVNGT0		XBYTE[0x275E]
#define 	xNEVVOL		XBYTE[0x275F]
//----------------------------------------------------
// VOICE RX FIFO Control (From I2S to MAC TX FIFO)
//----------------------------------------------------
#define 	xVRF_DAT		XBYTE[0x2760]
#define 	xVRF_MUT		XBYTE[0x2761]
#define 	xVRF_CTL		XBYTE[0x2762]
//------------------------
// VRFCTL
//------------------------
// [7:4]	: -
// [3]	: DMA Enable(MRxFIFO --> VRxFIFO)
// [2]	: MUTE
// [1] 	: Clear Write/Read Pointer
// [0]	: Initialize VRXFIFO[] to Mute Data
//------------------------
#define 	xVRF_RP		XBYTE[0x2763]
#define 	xVRF_WP		XBYTE[0x2764]
#define 	xVRF_SIZE		XBYTE[0x2765]
#define 	xVRF_HTHR		XBYTE[0x2766]
#define 	xVRF_LTHR		XBYTE[0x2767]
#define 	xVRF_ROOM		XBYTE[0x2768]
#define 	xVRF_2769		XBYTE[0x2769]
#define 	xVRF_STS		XBYTE[0x276A]
#define 	xVRD_SIZE		XBYTE[0x276B]
#define	xFEVOS			XBYTE[0x276C]
#define	xFEVNGT1		XBYTE[0x276D]
#define	xFEVNGT0		XBYTE[0x276E]
#define	xFEVVOL		XBYTE[0x276F]
//----------------------------------------------------
// VOICE IF
//----------------------------------------------------
#define	xVTFINTENA		XBYTE[0x2770]
//-----------------
// VTFINTENA
// [7]	: EMPTY
// [6]	: FULL
// [5]	: EMPTY_N
// [4]	: FULL_N
// [3]	: OVF
// [2]	: UDF
// [1]	: CDCPOP
// [0]	: PCMPOP
//-----------------
#define	xVRFINTENA		XBYTE[0x2771]
//-----------------
// VRFINTENA
// [7]	: EMPTY
// [6]	: FULL
// [5]	: EMPTY_N
// [4]	: FULL_N
// [3]	: OVF
// [2]	: UDF
// [1]	: CDCPOP
// [0]	: PCMPOP
//-----------------
#define	xVDMINTENA	XBYTE[0x2772]
//-----------------
// VDMINTENA
// [7]	: VTF Abnormal
// [6]	: VTF High Threshold
// [5]	: VTF Low Threshold
// [4]	: VTF DMA Done(I2SRX --> VTF --> MTF)
// [3]	: VRF Abnormal
// [2]	: VRF High Threshold
// [1]	: VRF Low Threshold
// [0]	: VRF DMA Done(I2STX <-- VRF <-- MRF)
//-----------------
#define	xVTFINTSRC		XBYTE[0x2773]
//-----------------
// VTFINTSRC
// [7]	: Empty
// [6]	: Full
// [5]	: Empty Neg
// [4]	: Full Neg
// [3]	: Overflow
// [2]	: Underflow
// [1]	: Codec Pop
// [0]	: PCM Pop
//-----------------
#define	xVRFINTSRC		XBYTE[0x2774]
//-----------------
// VRFINTSRC
// [7]	: Empty
// [6]	: Full
// [5]	: Empty Neg
// [4]	: Full Neg
// [3]	: Overflow
// [2]	: Underflow
// [1]	: Codec Push
// [0]	: PCM Push
//-----------------
#define	xVDMINTSRC		XBYTE[0x2775]
//-----------------
// VDMINTSRC
// [7]	: VTF Abnormal
// [6]	: VTF High Threshold
// [5]	: VTF Low Threshold
// [4]	: VTF DMA Done(I2SRX --> VTF --> MTF)
// [3]	: VRF Abnormal
// [2]	: VRF High Threshold
// [1]	: VRF Low Threshold
// [0]	: VRF DMA Done(I2STX <-- VRF <-- MRF)
//-----------------
#define	xVTFINTVAL		XBYTE[0x2776]
#define	xVRFINTVAL		XBYTE[0x2777]
//-----------------
// VRFINTVAL
// [7]	: Empty
// [6]	: Full
// [5]	: Empty Neg
// [4]	: Full Neg
// [3]	: Overflow
// [2]	: Underflow
// [1]	: Codec Push
// [0]	: PCM Push
//-----------------
#define	xVDMINTVAL		XBYTE[0x2778]
#define	xVCECFG		XBYTE[0x2779]

#define	xSRCCTL			XBYTE[0x277A]
#define	x277B			XBYTE[0x277B]
#define	xVSPMUT1		XBYTE[0x277C]
#define	xVSPMUT0		XBYTE[0x277D]
#define	xVSPCTL			XBYTE[0x277E]
//------------------------
// VSPCTL
//------------------------
// [7]	: -
// [6]	: DECMUT
// [5]	: DECINI
// [4] 	: DECB16
// [3]	: -
// [2]	: ENCMUT
// [1] 	: ENCINI
// [0]	: ENCB16
//------------------------
#define	x277F			XBYTE[0x277F]
//----------------------------------------------------
// Acoustic Echo Canceler (1)
//----------------------------------------------------
#define	xCONVTHR1		XBYTE[0x2780]
#define	xCONVTHR0		XBYTE[0x2781]
#define	xDIVRGTHR1		XBYTE[0x2782]
#define	xDIVRGTHR0		XBYTE[0x2783]
#define	xDTTHR1		XBYTE[0x2784]
#define	xDTTHR0		XBYTE[0x2785]
#define	xNLPSPD1		XBYTE[0x2786]
#define	xNLPSPD0		XBYTE[0x2787]
#define	x2788			XBYTE[0x2788]
#define	x2789			XBYTE[0x2789]
#define	xHDPLXTHR1		XBYTE[0x278A]
#define	xHDPLXTHR0		XBYTE[0x278B]
#define	xHDPLXSTCNT1	XBYTE[0x278C]
#define	xHDPLXSTCNT0	XBYTE[0x278D]
#define	xTDETTHR1		XBYTE[0x278E]
#define	xTDETTHR0		XBYTE[0x278F]
//----------------------------------------------------
// Acoustic Echo Canceler (2)
//----------------------------------------------------
#define	xTDETONCNT1	XBYTE[0x2790]
#define	xTDETONCNT0	XBYTE[0x2791]
#define	xTDETOFFCNT1	XBYTE[0x2792]
#define	xTDETOFFCNT0	XBYTE[0x2793]
#define	xTDETMU1		XBYTE[0x2794]
#define	xTDETMU0		XBYTE[0x2795]
#define	xINITOUTLEV1	XBYTE[0x2796]
#define	xINITOUTLEV0	XBYTE[0x2797]
#define	xINITCURGAIN3	XBYTE[0x2798]
#define	xINITCURGAIN2	XBYTE[0x2799]
#define	xINITCURGAIN1	XBYTE[0x279A]
#define	xINITCURGAIN0	XBYTE[0x279B]
#define	xGAINUPSPD1	XBYTE[0x279C]
#define	xGAINUPSPD0	XBYTE[0x279D]
#define	xGAINDNSPD1	XBYTE[0x279E]
#define	xGAINDNSPD0	XBYTE[0x279F]
//----------------------------------------------------
// Acoustic Echo Canceler (3)
//----------------------------------------------------
#define	xMINGAIN1		XBYTE[0x27A0]
#define	xMINGAIN0		XBYTE[0x27A1]
#define	xMAXGAIN1		XBYTE[0x27A2]
#define	xMAXGAIN0		XBYTE[0x27A3]
#define	xNTAPS1		XBYTE[0x27A4]
#define	xNTAPS0		XBYTE[0x27A5]
#define	xLMSMU1		XBYTE[0x27A6]
#define	xLMSMU0		XBYTE[0x27A7]
#define	xAEC_CTL		XBYTE[0x27A8]
#define	xAEC_STA		XBYTE[0x27A9]
#define	x27AA			XBYTE[0x27AA]
#define	x27AB			XBYTE[0x27AB]
#define	x27AC			XBYTE[0x27AC]
#define	x27AD			XBYTE[0x27AD]
#define	x27AE			XBYTE[0x27AE]
#define	x27AF			XBYTE[0x27AF]


//----------------------------------------------------
//	RF Register Set
//----------------------------------------------------
#define	PHY_BASE	0x2200
//----------------------------------------------------
// MODEM Command
//----------------------------------------------------
	#define	xPCMD0			XBYTE[PHY_BASE + 0x00]
	#define	xPCMD1			XBYTE[PHY_BASE + 0x01]
	#define	xPLLPD			XBYTE[PHY_BASE + 0x02]
	#define	xPLLPU			XBYTE[PHY_BASE + 0x03]
	#define	xRXRFPD		XBYTE[PHY_BASE + 0x04]
	#define	xRXRFPU		XBYTE[PHY_BASE + 0x05]
	#define	xTXRFPD		XBYTE[PHY_BASE + 0x06]
	#define	xTXRFPU		XBYTE[PHY_BASE + 0x07]
	#define	xRSVD08		XBYTE[PHY_BASE + 0x08]
	#define	xBIASPD		XBYTE[PHY_BASE + 0x09]
	#define	xBIASPU		XBYTE[PHY_BASE + 0x0A]
	#define	xCHNLSEL		XBYTE[PHY_BASE + 0x0B]
	#define	xRFCONCNF		XBYTE[PHY_BASE + 0x0C]
	#define	xGPCNF4		XBYTE[PHY_BASE + 0x0D]
	#define	xGPCNF5		XBYTE[PHY_BASE + 0x0E]

//----------------------------------------------------
// MODEM Config
//----------------------------------------------------
	#define	xMDMCNF		XBYTE[PHY_BASE + 0x10]
	#define	xRXFRM1		XBYTE[PHY_BASE + 0x11]
	#define	xTDCNF3		XBYTE[PHY_BASE + 0x13]	
	#define	xTDCNF0		XBYTE[PHY_BASE + 0x17]
	#define	xGPCNF0		XBYTE[PHY_BASE + 0x19]
	#define	xGPCNF1		XBYTE[PHY_BASE + 0x1A]
	#define	xGPCNF2		XBYTE[PHY_BASE + 0x1B]
	#define	xGPCNF3		XBYTE[PHY_BASE + 0x1C]
	#define	xTDCNF2		XBYTE[PHY_BASE + 0x1D]	

//----------------------------------------------------
// AGC
//----------------------------------------------------

	#define	xAGCCNF0		XBYTE[PHY_BASE + 0x20]
	#define	xAGCCNF1		XBYTE[PHY_BASE + 0x21]
	#define	xAGCCNF3		XBYTE[PHY_BASE + 0x23]
	#define	xAGCCNF5		XBYTE[PHY_BASE + 0x25]
	#define	xAGCCNF6		XBYTE[PHY_BASE + 0x26]	
	#define	xAGCCNF7		XBYTE[PHY_BASE + 0x27]
	#define	xAGCCNF8		XBYTE[PHY_BASE + 0x28]
	#define	xAGCCNF9		XBYTE[PHY_BASE + 0x29]
	#define	xAGCCNF10		XBYTE[PHY_BASE + 0x2A]
	#define	xAGCCNF11		XBYTE[PHY_BASE + 0x2B]
	#define	xAGCCNF12		XBYTE[PHY_BASE + 0x2C]
	#define	xAGCCNF15		XBYTE[PHY_BASE + 0x2F]	
	#define	xAGCCNF16		XBYTE[PHY_BASE + 0x30]	
	#define	xAGCCNF17		XBYTE[PHY_BASE + 0x31]
	#define	xAGCCNF18		XBYTE[PHY_BASE + 0x32]
	#define	xAGCCNF19		XBYTE[PHY_BASE + 0x33]
	#define	xAGCCNF22		XBYTE[PHY_BASE + 0x3A]
	#define	xAGCCNF23		XBYTE[PHY_BASE + 0x3B]
	#define	xAGCCNF24		XBYTE[PHY_BASE + 0x3C]
	#define	xAGCCNF26		XBYTE[PHY_BASE + 0x3E]

//----------------------------------------------------
// COR/TME/CCA Config
//----------------------------------------------------
	#define	xCORCNF0		XBYTE[PHY_BASE + 0x40]
	#define	xCORCNF1		XBYTE[PHY_BASE + 0x41]
	#define	xCORCNF2		XBYTE[PHY_BASE + 0x42]

//----------------------------------------------------
// Reserved Region
//----------------------------------------------------

//----------------------------------------------------
// Test Operation Config and Monitor
//----------------------------------------------------
	#define	xTST0			XBYTE[PHY_BASE + 0x60]
	#define	xTST1			XBYTE[PHY_BASE + 0x61]
	#define	xTST2			XBYTE[PHY_BASE + 0x62]
	#define	xTST13			XBYTE[PHY_BASE + 0x6D]
	#define	xTST14			XBYTE[PHY_BASE + 0x6E]
	#define	xTST15			XBYTE[PHY_BASE + 0x6F]

//----------------------------------------------------
// Status Monitor and Control
//----------------------------------------------------
	#define	xAGCSTS1		XBYTE[PHY_BASE + 0x73]
	#define	xAGCSTS2		XBYTE[PHY_BASE + 0x74]
	#define	xAGCSTS3		XBYTE[PHY_BASE + 0x75]
	#define	xINTCON		XBYTE[PHY_BASE + 0x77]	// bit[3]=RxEnd, bit[2]=RxStart, bit[1]=TxEnd, bit[0]=ModemOn
	#define	xINTIDX			XBYTE[PHY_BASE + 0x78]
	#define	xMONCON0		XBYTE[PHY_BASE + 0x79]
	#define	xINTSTS			XBYTE[PHY_BASE + 0x7E]	// bit[3:0] : 0=Modem-On, 1=Tx-End, 2=Rx-Start, 3=Rx-End

//----------------------------------------------------
// PLL Config
//----------------------------------------------------
	#define	xPLLADIV		XBYTE[PHY_BASE + 0x80]
	#define	xPLLRDIV		XBYTE[PHY_BASE + 0x81]	
	#define	xPLLBDIV		XBYTE[PHY_BASE + 0x82]
	#define	xPLLFRAC3		XBYTE[PHY_BASE + 0x86]
	#define	xPLLFRAC4		XBYTE[PHY_BASE + 0x87]
	#define	xPLLADFC		XBYTE[PHY_BASE + 0x89]
	#define	xPLLLD			XBYTE[PHY_BASE + 0x8A]
	#define	xPLLCP			XBYTE[PHY_BASE + 0x8B]
	#define	xPLLVCO			XBYTE[PHY_BASE + 0x8C]
	#define	xPLLVC			XBYTE[PHY_BASE + 0x8D]
	#define	xPLLDIV			XBYTE[PHY_BASE + 0x8E]
	#define	xPLLBUF			XBYTE[PHY_BASE + 0x8F]

//----------------------------------------------------
// RF RX Path Config
//----------------------------------------------------
	#define	xRXLNA			XBYTE[PHY_BASE + 0x90]
	#define	xRXMIX			XBYTE[PHY_BASE + 0x91]
	#define	xRXIP2I			XBYTE[PHY_BASE + 0x92]
	#define	xRXIP2Q			XBYTE[PHY_BASE + 0x93]
	#define	xRXBBAMP		XBYTE[PHY_BASE + 0x94]
	#define	xRXRSSI			XBYTE[PHY_BASE + 0x95]
	#define	xRXVGA			XBYTE[PHY_BASE + 0x97]
	#define	xCTLVGA		XBYTE[PHY_BASE + 0x98]
	#define	xCTLVGA2		XBYTE[PHY_BASE + 0x99]
	#define	xPLLLF1			XBYTE[PHY_BASE + 0x9B]
	#define	xPLLLF2			XBYTE[PHY_BASE + 0x9C]
	#define	xPLLLF3			XBYTE[PHY_BASE + 0x9D]
	#define	xVRXLPF			XBYTE[PHY_BASE + 0x9E]
	#define	xCHIPID			XBYTE[PHY_BASE + 0x9F]

//----------------------------------------------------
// RF TX Path Config
//----------------------------------------------------
	#define	xTXPA			XBYTE[PHY_BASE + 0xA0]
	#define	xTXDA			XBYTE[PHY_BASE + 0xA1]
	#define	xTXMIX			XBYTE[PHY_BASE + 0xA2]
	#define	xTXLPF			XBYTE[PHY_BASE + 0xA4]
	#define	xMEAS2			XBYTE[PHY_BASE + 0xA6]
	#define	xBIAS			XBYTE[PHY_BASE + 0xA7]
	#define	xSADCCON		XBYTE[PHY_BASE + 0xAB]
	#define	xSADCVALH		XBYTE[PHY_BASE + 0xAC]
	#define	xSADCVALL		XBYTE[PHY_BASE + 0xAD]
	#define	xSADCBIASH		XBYTE[PHY_BASE + 0xAE]
	#define	xSADCBIASL		XBYTE[PHY_BASE + 0xAF]

	#define	xDCCCON		XBYTE[PHY_BASE + 0xB0]
	#define	xDCCCNF		XBYTE[PHY_BASE + 0xB5]

//----------------------------------------------------
// Clock/Reset/Power-Down Control
//----------------------------------------------------

	#define	xCLKON0		XBYTE[PHY_BASE + 0xC0]
	#define	xCLKDIV0		XBYTE[PHY_BASE + 0xC3]
	#define	xCLKON1		XBYTE[PHY_BASE + 0xC4]
	#define	xCLKON2		XBYTE[PHY_BASE + 0xC8]
	#define	xSWRST			XBYTE[PHY_BASE + 0xCC]

//----------------------------------------------------
// 3V Logic
//----------------------------------------------------

	#define	xPDM			XBYTE[PHY_BASE + 0xF0]
	#define	xPDCON			XBYTE[PHY_BASE + 0xF1]
	#define	xRCOSC1		XBYTE[PHY_BASE + 0xF2]
	#define	xRCOSC2		XBYTE[PHY_BASE + 0xF3]
	#define	xRTDLY			XBYTE[PHY_BASE + 0xF4]
	#define	xRTCON			XBYTE[PHY_BASE + 0xF5]
	#define	xRTINT1			XBYTE[PHY_BASE + 0xF6]
	#define	xRTINT0			XBYTE[PHY_BASE + 0xF7]
	#define	xCKPLL			XBYTE[PHY_BASE + 0xF8]

	
//----------------------------------------------------
// End of Register Set
//----------------------------------------------------
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