unsigned long diff_nsec;	unsigned long factor;	/* Setup the timer:  We don't want to generate interrupts, just	 * have it count down at its natural rate.	 */	ctrl_outb(0, TMU_TSTR);#if !defined(CONFIG_CPU_SUBTYPE_SH7300)	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);#endif	ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);	ctrl_outl(0xffffffff, TMU0_TCOR);	ctrl_outl(0xffffffff, TMU0_TCNT);	rtc_get_time(&ts2);	do {		rtc_get_time(&ts1);	} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);	/* actually start the timer */	ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);	do {		rtc_get_time(&ts2);	} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);	freq = 0xffffffff - ctrl_inl(TMU0_TCNT);	if (ts2.tv_nsec < ts1.tv_nsec) {		ts2.tv_nsec += 1000000000;		ts2.tv_sec--;	}	diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);	/* this should work well if the RTC has a precision of n Hz, where	 * n is an integer.  I don't think we have to worry about the other	 * cases. */	factor = (1000000000 + diff_nsec/2) / diff_nsec;	if (factor * diff_nsec > 1100000000 ||	    factor * diff_nsec <  900000000)		panic("weird RTC (diff_nsec %ld)", diff_nsec);	return freq * factor;}void (*board_time_init)(void) = 0;void (*board_timer_setup)(struct irqaction *irq) = 0;static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ;static int __init sh_pclk_setup(char *str){        unsigned int freq;	if (get_option(&str, &freq))		sh_pclk_freq = freq;	return 1;}__setup("sh_pclk=", sh_pclk_setup);static struct irqaction irq0  = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};void get_current_frequency_divisors(unsigned int *ifc, unsigned int *bfc, unsigned int *pfc){	unsigned int frqcr = ctrl_inw(FRQCR);#if defined(CONFIG_CPU_SH3)#if defined(CONFIG_CPU_SUBTYPE_SH7300)	*ifc = md_table[((frqcr & 0x0070) >> 4)];	*bfc = md_table[((frqcr & 0x0700) >> 8)];	*pfc = md_table[frqcr & 0x0007];#elif defined(CONFIG_CPU_SUBTYPE_SH7705)	*bfc = stc_multipliers[(frqcr & 0x0300) >> 8];	*ifc = ifc_divisors[(frqcr & 0x0030) >> 4];	*pfc = pfc_divisors[frqcr & 0x0003];#else	unsigned int tmp;	tmp  = (frqcr & 0x8000) >> 13;	tmp |= (frqcr & 0x0030) >>  4;	*bfc = stc_multipliers[tmp];	tmp  = (frqcr & 0x4000)  >> 12;	tmp |= (frqcr & 0x000c) >> 2;	*ifc = ifc_divisors[tmp];	tmp  = (frqcr & 0x2000) >> 11;	tmp |= frqcr & 0x0003;	*pfc = pfc_divisors[tmp];#endif#elif defined(CONFIG_CPU_SH4)	*ifc = ifc_divisors[(frqcr >> 6) & 0x0007];	*bfc = bfc_divisors[(frqcr >> 3) & 0x0007];	*pfc = pfc_divisors[frqcr & 0x0007];#endif}/* * This bit of ugliness builds up accessor routines to get at both * the divisors and the physical values. */#define _FREQ_TABLE(x) \	unsigned int get_##x##_divisor(unsigned int value) 	\		{ return x##_divisors[value]; }			\								\	unsigned int get_##x##_value(unsigned int divisor)	\		{ return x##_values[(divisor - 1)]; }_FREQ_TABLE(ifc);_FREQ_TABLE(bfc);_FREQ_TABLE(pfc);#ifdef CONFIG_CPU_SUBTYPE_ST40STB1/* The ST40 divisors are totally different so we set the cpu data** clocks using a different algorithm**** I've just plugged this from the 2.4 code - Alex Bennee <kernel-hacker@bennee.com>*/#define CCN_PVR_CHIP_SHIFT 24#define CCN_PVR_CHIP_MASK  0xff#define CCN_PVR_CHIP_ST40STB1 0x4struct frqcr_data {    unsigned short frqcr;    struct {	unsigned char multiplier;	unsigned char divisor;    } factor[3];};static struct frqcr_data st40_frqcr_table[] = {    { 0x000, {{1,1}, {1,1}, {1,2}}},    { 0x002, {{1,1}, {1,1}, {1,4}}},    { 0x004, {{1,1}, {1,1}, {1,8}}},    { 0x008, {{1,1}, {1,2}, {1,2}}},    { 0x00A, {{1,1}, {1,2}, {1,4}}},    { 0x00C, {{1,1}, {1,2}, {1,8}}},    { 0x011, {{1,1}, {2,3}, {1,6}}},    { 0x013, {{1,1}, {2,3}, {1,3}}},    { 0x01A, {{1,1}, {1,2}, {1,4}}},    { 0x01C, {{1,1}, {1,2}, {1,8}}},    { 0x023, {{1,1}, {2,3}, {1,3}}},    { 0x02C, {{1,1}, {1,2}, {1,8}}},    { 0x048, {{1,2}, {1,2}, {1,4}}},    { 0x04A, {{1,2}, {1,2}, {1,6}}},    { 0x04C, {{1,2}, {1,2}, {1,8}}},    { 0x05A, {{1,2}, {1,3}, {1,6}}},    { 0x05C, {{1,2}, {1,3}, {1,6}}},    { 0x063, {{1,2}, {1,4}, {1,4}}},    { 0x06C, {{1,2}, {1,4}, {1,8}}},    { 0x091, {{1,3}, {1,3}, {1,6}}},    { 0x093, {{1,3}, {1,3}, {1,6}}},    { 0x0A3, {{1,3}, {1,6}, {1,6}}},    { 0x0DA, {{1,4}, {1,4}, {1,8}}},    { 0x0DC, {{1,4}, {1,4}, {1,8}}},    { 0x0EC, {{1,4}, {1,8}, {1,8}}},    { 0x123, {{1,4}, {1,4}, {1,8}}},    { 0x16C, {{1,4}, {1,8}, {1,8}}},};struct memclk_data {    unsigned char multiplier;    unsigned char divisor;};static struct memclk_data st40_memclk_table[8] = {    {1,1},	// 000    {1,2},	// 001    {1,3},	// 010    {2,3},	// 011    {1,4},	// 100    {1,6},	// 101    {1,8},	// 110    {1,8}	// 111};static void st40_specific_time_init(unsigned int module_clock, unsigned short frqcr){    unsigned int cpu_clock, master_clock, bus_clock, memory_clock;    struct frqcr_data *d;    int a;    unsigned long memclkcr;    struct memclk_data *e;    for (a=0; a<ARRAY_SIZE(st40_frqcr_table); a++) {	d = &st40_frqcr_table[a];	if (d->frqcr == (frqcr & 0x1ff))	    break;    }    if (a == ARRAY_SIZE(st40_frqcr_table)) {	d = st40_frqcr_table;	printk("ERROR: Unrecognised FRQCR value (0x%x), using default multipliers\n",frqcr);    }    memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR);    e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK];    printk("Clock multipliers: CPU: %d/%d Bus: %d/%d Mem: %d/%d Periph: %d/%d\n",	    d->factor[0].multiplier, d->factor[0].divisor,	    d->factor[1].multiplier, d->factor[1].divisor,	    e->multiplier,           e->divisor,	    d->factor[2].multiplier, d->factor[2].divisor);    master_clock = module_clock * d->factor[2].divisor    / d->factor[2].multiplier;    bus_clock    = master_clock * d->factor[1].multiplier / d->factor[1].divisor;    memory_clock = master_clock * e->multiplier           / e->divisor;    cpu_clock    = master_clock * d->factor[0].multiplier / d->factor[0].divisor;    current_cpu_data.cpu_clock    = cpu_clock;    current_cpu_data.master_clock = master_clock;    current_cpu_data.bus_clock    = bus_clock;    current_cpu_data.memory_clock = memory_clock;    current_cpu_data.module_clock = module_clock;}#endifvoid __init time_init(void){	unsigned int timer_freq = 0;	unsigned int ifc, pfc, bfc;	unsigned long interval;#ifdef CONFIG_CPU_SUBTYPE_ST40STB1	unsigned long pvr;	unsigned short frqcr;#endif	if (board_time_init)		board_time_init();	/*	 * If we don't have an RTC (such as with the SH7300), don't attempt to	 * probe the timer frequency. Rely on an either hardcoded peripheral	 * clock value, or on the sh_pclk command line option. Note that we	 * still need to have CONFIG_SH_PCLK_FREQ set in order for things like	 * CLOCK_TICK_RATE to be sane.	 */	current_cpu_data.module_clock = sh_pclk_freq;#ifdef CONFIG_SH_PCLK_CALC	/* XXX: Switch this over to a more generic test. */	{		unsigned int freq;		/* 		 * If we've specified a peripheral clock frequency, and we have		 * an RTC, compare it against the autodetected value. Complain		 * if there's a mismatch.		 *		 * Note: We should allow for some high and low watermarks for		 * the frequency here (compensating for potential drift), as		 * otherwise we'll likely end up triggering this essentially		 * on every boot.		 */		timer_freq = get_timer_frequency();		freq = timer_freq * 4;		if (sh_pclk_freq && (sh_pclk_freq/100*99 > freq || sh_pclk_freq/100*101 < freq)) {			printk(KERN_NOTICE "Calculated peripheral clock value "			       "%d differs from sh_pclk value %d, fixing..\n",			       freq, sh_pclk_freq);			current_cpu_data.module_clock = freq;		}	}#endif#ifdef CONFIG_CPU_SUBTYPE_ST40STB1	pvr = ctrl_inl(CCN_PVR);	frqcr = ctrl_inw(FRQCR);	printk("time.c ST40 Probe: PVR %08lx, FRQCR %04hx\n", pvr, frqcr);	if (((pvr >>CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1)	    st40_specific_time_init(current_cpu_data.module_clock, frqcr);	else#endif	    get_current_frequency_divisors(&ifc, &bfc, &pfc);	if (rtc_get_time)		rtc_get_time(&xtime);	else {         	xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);         	xtime.tv_nsec = 0;	}        set_normalized_timespec(&wall_to_monotonic,                                -xtime.tv_sec, -xtime.tv_nsec);	if (board_timer_setup) {		board_timer_setup(&irq0);	} else {		setup_irq(TIMER_IRQ, &irq0);	}	/*	** for ST40 chips the current_cpu_data should already be set	** so not having valid pfc/bfc/ifc shouldn't be a problem	*/	if (!current_cpu_data.master_clock)		current_cpu_data.master_clock = current_cpu_data.module_clock * pfc;	if (!current_cpu_data.bus_clock)		current_cpu_data.bus_clock = current_cpu_data.master_clock / bfc;	if (!current_cpu_data.cpu_clock)		current_cpu_data.cpu_clock = current_cpu_data.master_clock / ifc;	printk("CPU clock: %d.%02dMHz\n",	       (current_cpu_data.cpu_clock / 1000000),	       (current_cpu_data.cpu_clock % 1000000)/10000);	printk("Bus clock: %d.%02dMHz\n",	       (current_cpu_data.bus_clock / 1000000),	       (current_cpu_data.bus_clock % 1000000)/10000);#ifdef CONFIG_CPU_SUBTYPE_ST40STB1	printk("Memory clock: %d.%02dMHz\n",	       (current_cpu_data.memory_clock / 1000000),	       (current_cpu_data.memory_clock % 1000000)/10000);#endif	printk("Module clock: %d.%02dMHz\n",	       (current_cpu_data.module_clock / 1000000),	       (current_cpu_data.module_clock % 1000000)/10000);#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)	interval = ((current_cpu_data.module_clock/4 + HZ/2) / HZ) - 1;#else	interval = (current_cpu_data.module_clock/4 + HZ/2) / HZ;#endif	printk("Interval = %ld\n", interval);	/* Start TMU0 */	ctrl_outb(0, TMU_TSTR);#if !defined(CONFIG_CPU_SUBTYPE_SH7300)	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);#endif	ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);	ctrl_outl(interval, TMU0_TCOR);	ctrl_outl(interval, TMU0_TCNT);	ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);#if defined(CONFIG_SH_KGDB)	/*	 * Set up kgdb as requested. We do it here because the serial	 * init uses the timer vars we just set up for figuring baud.	 */	kgdb_init();#endif}