/*     Driver for Zarlink MT312 Satellite Channel Decoder    Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>    This program is free software; you can redistribute it and/or modify    it under the terms of the GNU General Public License as published by    the Free Software Foundation; either version 2 of the License, or    (at your option) any later version.    This program is distributed in the hope that it will be useful,    but WITHOUT ANY WARRANTY; without even the implied warranty of    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    GNU General Public License for more details.    You should have received a copy of the GNU General Public License    along with this program; if not, write to the Free Software    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.    References:    http://products.zarlink.com/product_profiles/MT312.htm    http://products.zarlink.com/product_profiles/SL1935.htm*/#include <linux/delay.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/module.h>#include "dvb_frontend.h"#include "mt312.h"#define I2C_ADDR_MT312		0x0e#define I2C_ADDR_SL1935		0x61#define I2C_ADDR_TSA5059	0x61#define MT312_DEBUG		0#define MT312_SYS_CLK		90000000UL	/* 90 MHz */#define MT312_LPOWER_SYS_CLK	60000000UL	/* 60 MHz */#define MT312_PLL_CLK		10000000UL	/* 10 MHz *//* number of active frontends */static int mt312_count = 0;#if MT312_DEBUG == 0#define dprintk(x...)#elsestatic int debug = 0;#define dprintk if(debug == 1) printk#endifstatic struct dvb_frontend_info mt312_info = {	.name = "Zarlink MT312",	.type = FE_QPSK,	.frequency_min = 950000,	.frequency_max = 2150000,	.frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,	/*.frequency_tolerance = 29500,         FIXME: binary compatibility waste? */	.symbol_rate_min = MT312_SYS_CLK / 128,	.symbol_rate_max = MT312_SYS_CLK / 2,	/*.symbol_rate_tolerance = 500,         FIXME: binary compatibility waste? 2% */	.notifier_delay = 0,	.caps =	    FE_CAN_INVERSION_AUTO | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |	    FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |	    FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |             FE_CAN_RECOVER};static int mt312_read(struct dvb_i2c_bus *i2c,		      const enum mt312_reg_addr reg, void *buf,		      const size_t count){	int ret;	struct i2c_msg msg[2];	u8 regbuf[1] = { reg };	msg[0].addr = I2C_ADDR_MT312;	msg[0].flags = 0;	msg[0].buf = regbuf;	msg[0].len = 1;	msg[1].addr = I2C_ADDR_MT312;	msg[1].flags = I2C_M_RD;	msg[1].buf = buf;	msg[1].len = count;	ret = i2c->xfer(i2c, msg, 2);	if ((ret != 2) && (mt312_count != 0)) {		printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);		return -EREMOTEIO;	}#if MT312_DEBUG	if(debug) {		int i;		printk(KERN_INFO "R(%d):", reg & 0x7f);		for (i = 0; i < count; i++)			printk(" %02x", ((const u8 *) buf)[i]);		printk("\n");	}#endif	return 0;}static int mt312_write(struct dvb_i2c_bus *i2c,		       const enum mt312_reg_addr reg, const void *src,		       const size_t count){	int ret;	u8 buf[count + 1];	struct i2c_msg msg;#if MT312_DEBUG	if(debug) {		int i;		printk(KERN_INFO "W(%d):", reg & 0x7f);		for (i = 0; i < count; i++)			printk(" %02x", ((const u8 *) src)[i]);		printk("\n");	}#endif	buf[0] = reg;	memcpy(&buf[1], src, count);	msg.addr = I2C_ADDR_MT312;	msg.flags = 0;	msg.buf = buf;	msg.len = count + 1;	ret = i2c->xfer(i2c, &msg, 1);	if (ret != 1) {		printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);		return -EREMOTEIO;	}	return 0;}static inline int mt312_readreg(struct dvb_i2c_bus *i2c,				const enum mt312_reg_addr reg, u8 * val){	return mt312_read(i2c, reg, val, 1);}static inline int mt312_writereg(struct dvb_i2c_bus *i2c,				 const enum mt312_reg_addr reg, const u8 val){	return mt312_write(i2c, reg, &val, 1);}static int mt312_pll_write(struct dvb_i2c_bus *i2c, const u8 addr,			   u8 * buf, const u8 len){	int ret;	struct i2c_msg msg;	msg.addr = addr;	msg.flags = 0;	msg.buf = buf;	msg.len = len;	if ((ret = mt312_writereg(i2c, GPP_CTRL, 0x40)) < 0)		return ret;	if ((ret = i2c->xfer(i2c, &msg, 1)) != 1)		printk(KERN_ERR "%s: i/o error (ret == %d)\n", __FUNCTION__, ret);	if ((ret = mt312_writereg(i2c, GPP_CTRL, 0x00)) < 0)		return ret;	return 0;}static inline u32 mt312_div(u32 a, u32 b){	return (a + (b / 2)) / b;}static int sl1935_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq, u32 sr){	/* 155 uA, Baseband Path B */	u8 buf[4] = { 0x00, 0x00, 0x80, 0x00 };	u8 exp;	u32 ref;	u32 div;	if (sr < 10000000) {	/* 1-10 MSym/s: ratio 2 ^ 3 */		exp = 3;		buf[2] |= 0x40;	/* 690 uA */	} else if (sr < 15000000) {	/* 10-15 MSym/s: ratio 2 ^ 4 */		exp = 4;		buf[2] |= 0x20;	/* 330 uA */	} else {		/* 15-45 MSym/s: ratio 2 ^ 7 */		exp = 7;		buf[3] |= 0x08;	/* Baseband Path A */	}	div = mt312_div(MT312_PLL_CLK, 1 << exp);	ref = mt312_div(freq * 1000, div);	mt312_info.frequency_stepsize = mt312_div(div, 1000);	buf[0] = (ref >> 8) & 0x7f;	buf[1] = (ref >> 0) & 0xff;	buf[2] |= (exp - 1);	if (freq < 1550000)		buf[3] |= 0x10;	dprintk(KERN_INFO "synth dword = %02x%02x%02x%02x\n", buf[0],	       buf[1], buf[2], buf[3]);	return mt312_pll_write(i2c, I2C_ADDR_SL1935, buf, sizeof(buf));}static int tsa5059_set_tv_freq(struct dvb_i2c_bus *i2c, u32 freq, u32 sr){	u8 buf[4];	u32 ref = mt312_div(freq, 125);	buf[0] = (ref >> 8) & 0x7f;	buf[1] = (ref >> 0) & 0xff;	buf[2] = 0x84 | ((ref >> 10) & 0x60);	buf[3] = 0x80;		if (freq < 1550000)		buf[3] |= 0x02;	dprintk(KERN_INFO "synth dword = %02x%02x%02x%02x\n", buf[0],	       buf[1], buf[2], buf[3]);	return mt312_pll_write(i2c, I2C_ADDR_TSA5059, buf, sizeof(buf));}static int mt312_reset(struct dvb_i2c_bus *i2c, const u8 full){	return mt312_writereg(i2c, RESET, full ? 0x80 : 0x40);}static int mt312_init(struct dvb_i2c_bus *i2c, const long id, u8 pll){	int ret;	u8 buf[2];	/* wake up */	if ((ret = mt312_writereg(i2c, CONFIG, (pll == 60 ? 0x88 : 0x8c))) < 0)		return ret;	/* wait at least 150 usec */	udelay(150);	/* full reset */	if ((ret = mt312_reset(i2c, 1)) < 0)		return ret;// Per datasheet, write correct values. 09/28/03 ACCJr.// If we don't do this, we won't get FE_HAS_VITERBI in the VP310.	{		u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00};		if ((ret = mt312_write(i2c, VIT_SETUP, buf_def, sizeof(buf_def))) < 0)			return ret;	}	/* SYS_CLK */	buf[0] = mt312_div((pll == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000);	/* DISEQC_RATIO */	buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);	if ((ret = mt312_write(i2c, SYS_CLK, buf, sizeof(buf))) < 0)		return ret;	if ((ret = mt312_writereg(i2c, SNR_THS_HIGH, 0x32)) < 0)		return ret;	if ((ret = mt312_writereg(i2c, OP_CTRL, 0x53)) < 0)		return ret;	/* TS_SW_LIM */	buf[0] = 0x8c;	buf[1] = 0x98;	if ((ret = mt312_write(i2c, TS_SW_LIM_L, buf, sizeof(buf))) < 0)		return ret;	if ((ret = mt312_writereg(i2c, CS_SW_LIM, 0x69)) < 0)		return ret;	return 0;}static int mt312_send_master_cmd(struct dvb_i2c_bus *i2c,				 const struct dvb_diseqc_master_cmd *c){	int ret;	u8 diseqc_mode;	if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))		return -EINVAL;	if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)		return ret;	if ((ret =	     mt312_write(i2c, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)		return ret;	if ((ret =	     mt312_writereg(i2c, DISEQC_MODE,			    (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)			    | 0x04)) < 0)		return ret;	/* set DISEQC_MODE[2:0] to zero if a return message is expected */	if (c->msg[0] & 0x02)		if ((ret =		     mt312_writereg(i2c, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)			return ret;	return 0;}static int mt312_recv_slave_reply(struct dvb_i2c_bus *i2c,				  struct dvb_diseqc_slave_reply *r){	/* TODO */	return -EOPNOTSUPP;}static int mt312_send_burst(struct dvb_i2c_bus *i2c, const fe_sec_mini_cmd_t c){	const u8 mini_tab[2] = { 0x02, 0x03 };	int ret;	u8 diseqc_mode;	if (c > SEC_MINI_B)		return -EINVAL;	if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)		return ret;	if ((ret =	     mt312_writereg(i2c, DISEQC_MODE,			    (diseqc_mode & 0x40) | mini_tab[c])) < 0)		return ret;	return 0;}static int mt312_set_tone(struct dvb_i2c_bus *i2c, const fe_sec_tone_mode_t t){	const u8 tone_tab[2] = { 0x01, 0x00 };	int ret;	u8 diseqc_mode;	if (t > SEC_TONE_OFF)		return -EINVAL;	if ((ret = mt312_readreg(i2c, DISEQC_MODE, &diseqc_mode)) < 0)		return ret;	if ((ret =	     mt312_writereg(i2c, DISEQC_MODE,			    (diseqc_mode & 0x40) | tone_tab[t])) < 0)		return ret;	return 0;}static int mt312_set_voltage(struct dvb_i2c_bus *i2c, const fe_sec_voltage_t v){	const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };	if (v > SEC_VOLTAGE_OFF)		return -EINVAL;	return mt312_writereg(i2c, DISEQC_MODE, volt_tab[v]);}static int mt312_read_status(struct dvb_i2c_bus *i2c, fe_status_t *s, const long id){	int ret;	u8 status[3], vit_mode;	*s = 0;	if ((ret = mt312_read(i2c, QPSK_STAT_H, status, sizeof(status))) < 0)		return ret;	dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);	if (status[0] & 0xc0)		*s |= FE_HAS_SIGNAL;	/* signal noise ratio */	if (status[0] & 0x04)		*s |= FE_HAS_CARRIER;	/* qpsk carrier lock */	if (status[2] & 0x02)		*s |= FE_HAS_VITERBI;	/* viterbi lock */	if (status[2] & 0x04)		*s |= FE_HAS_SYNC;	/* byte align lock */	if (status[0] & 0x01)		*s |= FE_HAS_LOCK;	/* qpsk lock */	// VP310 doesn't have AUTO, so we "implement it here" ACCJr	if ((id == ID_VP310) && !(status[0] & 0x01)) {