/* * linux/drivers/ide/ide-pmac.c * * Support for IDE interfaces on PowerMacs. * These IDE interfaces are memory-mapped and have a DBDMA channel * for doing DMA. * *  Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt * *  This program is free software; you can redistribute it and/or *  modify it under the terms of the GNU General Public License *  as published by the Free Software Foundation; either version *  2 of the License, or (at your option) any later version. * * Some code taken from drivers/ide/ide-dma.c: * *  Copyright (c) 1995-1998  Mark Lord * * TODO: - Use pre-calculated (kauai) timing tables all the time and * get rid of the "rounded" tables used previously, so we have the * same table format for all controllers and can then just have one * big table *  */#include <linux/config.h>#include <linux/types.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/init.h>#include <linux/delay.h>#include <linux/ide.h>#include <linux/notifier.h>#include <linux/reboot.h>#include <linux/pci.h>#include <linux/adb.h>#include <linux/pmu.h>#include <asm/prom.h>#include <asm/io.h>#include <asm/dbdma.h>#include <asm/ide.h>#include <asm/pci-bridge.h>#include <asm/machdep.h>#include <asm/pmac_feature.h>#include <asm/sections.h>#include <asm/irq.h>#ifndef CONFIG_PPC64#include <asm/mediabay.h>#endif#include "ide-timing.h"extern void ide_do_request(ide_hwgroup_t *hwgroup, int masked_irq);#define IDE_PMAC_DEBUG#define DMA_WAIT_TIMEOUT	50typedef struct pmac_ide_hwif {	unsigned long			regbase;	int				irq;	int				kind;	int				aapl_bus_id;	int				cable_80 : 1;	int				mediabay : 1;	int				broken_dma : 1;	int				broken_dma_warn : 1;	struct device_node*		node;	struct macio_dev		*mdev;	u32				timings[4];#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC	/* Those fields are duplicating what is in hwif. We currently	 * can't use the hwif ones because of some assumptions that are	 * beeing done by the generic code about the kind of dma controller	 * and format of the dma table. This will have to be fixed though.	 */	volatile struct dbdma_regs*	dma_regs;	struct dbdma_cmd*		dma_table_cpu;	dma_addr_t			dma_table_dma;	struct scatterlist*		sg_table;	int				sg_nents;	int				sg_dma_direction;#endif	} pmac_ide_hwif_t;static pmac_ide_hwif_t pmac_ide[MAX_HWIFS] __pmacdata;static int pmac_ide_count;enum {	controller_ohare,	/* OHare based */	controller_heathrow,	/* Heathrow/Paddington */	controller_kl_ata3,	/* KeyLargo ATA-3 */	controller_kl_ata4,	/* KeyLargo ATA-4 */	controller_un_ata6,	/* UniNorth2 ATA-6 */	controller_k2_ata6	/* K2 ATA-6 */};static const char* model_name[] = {	"OHare ATA",		/* OHare based */	"Heathrow ATA",		/* Heathrow/Paddington */	"KeyLargo ATA-3",	/* KeyLargo ATA-3 (MDMA only) */	"KeyLargo ATA-4",	/* KeyLargo ATA-4 (UDMA/66) */	"UniNorth ATA-6",	/* UniNorth2 ATA-6 (UDMA/100) */	"K2 ATA-6",		/* K2 ATA-6 (UDMA/100) */};/* * Extra registers, both 32-bit little-endian */#define IDE_TIMING_CONFIG	0x200#define IDE_INTERRUPT		0x300/* Kauai (U2) ATA has different register setup */#define IDE_KAUAI_PIO_CONFIG	0x200#define IDE_KAUAI_ULTRA_CONFIG	0x210#define IDE_KAUAI_POLL_CONFIG	0x220/* * Timing configuration register definitions *//* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */#define SYSCLK_TICKS(t)		(((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)#define SYSCLK_TICKS_66(t)	(((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)#define IDE_SYSCLK_NS		30	/* 33Mhz cell */#define IDE_SYSCLK_66_NS	15	/* 66Mhz cell *//* 100Mhz cell, found in Uninorth 2. I don't have much infos about * this one yet, it appears as a pci device (106b/0033) on uninorth * internal PCI bus and it's clock is controlled like gem or fw. It * appears to be an evolution of keylargo ATA4 with a timing register * extended to 2 32bits registers and a similar DBDMA channel. Other * registers seem to exist but I can't tell much about them. *  * So far, I'm using pre-calculated tables for this extracted from * the values used by the MacOS X driver. *  * The "PIO" register controls PIO and MDMA timings, the "ULTRA" * register controls the UDMA timings. At least, it seems bit 0 * of this one enables UDMA vs. MDMA, and bits 4..7 are the * cycle time in units of 10ns. Bits 8..15 are used by I don't * know their meaning yet */#define TR_100_PIOREG_PIO_MASK		0xff000fff#define TR_100_PIOREG_MDMA_MASK		0x00fff000#define TR_100_UDMAREG_UDMA_MASK	0x0000ffff#define TR_100_UDMAREG_UDMA_EN		0x00000001/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on * 40 connector cable and to 4 on 80 connector one. * Clock unit is 15ns (66Mhz) *  * 3 Values can be programmed: *  - Write data setup, which appears to match the cycle time. They *    also call it DIOW setup. *  - Ready to pause time (from spec) *  - Address setup. That one is weird. I don't see where exactly *    it fits in UDMA cycles, I got it's name from an obscure piece *    of commented out code in Darwin. They leave it to 0, we do as *    well, despite a comment that would lead to think it has a *    min value of 45ns. * Apple also add 60ns to the write data setup (or cycle time ?) on * reads. */#define TR_66_UDMA_MASK			0xfff00000#define TR_66_UDMA_EN			0x00100000 /* Enable Ultra mode for DMA */#define TR_66_UDMA_ADDRSETUP_MASK	0xe0000000 /* Address setup */#define TR_66_UDMA_ADDRSETUP_SHIFT	29#define TR_66_UDMA_RDY2PAUS_MASK	0x1e000000 /* Ready 2 pause time */#define TR_66_UDMA_RDY2PAUS_SHIFT	25#define TR_66_UDMA_WRDATASETUP_MASK	0x01e00000 /* Write data setup time */#define TR_66_UDMA_WRDATASETUP_SHIFT	21#define TR_66_MDMA_MASK			0x000ffc00#define TR_66_MDMA_RECOVERY_MASK	0x000f8000#define TR_66_MDMA_RECOVERY_SHIFT	15#define TR_66_MDMA_ACCESS_MASK		0x00007c00#define TR_66_MDMA_ACCESS_SHIFT		10#define TR_66_PIO_MASK			0x000003ff#define TR_66_PIO_RECOVERY_MASK		0x000003e0#define TR_66_PIO_RECOVERY_SHIFT	5#define TR_66_PIO_ACCESS_MASK		0x0000001f#define TR_66_PIO_ACCESS_SHIFT		0/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo * Can do pio & mdma modes, clock unit is 30ns (33Mhz) *  * The access time and recovery time can be programmed. Some older * Darwin code base limit OHare to 150ns cycle time. I decided to do * the same here fore safety against broken old hardware ;) * The HalfTick bit, when set, adds half a clock (15ns) to the access * time and removes one from recovery. It's not supported on KeyLargo * implementation afaik. The E bit appears to be set for PIO mode 0 and * is used to reach long timings used in this mode. */#define TR_33_MDMA_MASK			0x003ff800#define TR_33_MDMA_RECOVERY_MASK	0x001f0000#define TR_33_MDMA_RECOVERY_SHIFT	16#define TR_33_MDMA_ACCESS_MASK		0x0000f800#define TR_33_MDMA_ACCESS_SHIFT		11#define TR_33_MDMA_HALFTICK		0x00200000#define TR_33_PIO_MASK			0x000007ff#define TR_33_PIO_E			0x00000400#define TR_33_PIO_RECOVERY_MASK		0x000003e0#define TR_33_PIO_RECOVERY_SHIFT	5#define TR_33_PIO_ACCESS_MASK		0x0000001f#define TR_33_PIO_ACCESS_SHIFT		0/* * Interrupt register definitions */#define IDE_INTR_DMA			0x80000000#define IDE_INTR_DEVICE			0x40000000#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC/* Rounded Multiword DMA timings *  * I gave up finding a generic formula for all controller * types and instead, built tables based on timing values * used by Apple in Darwin's implementation. */struct mdma_timings_t {	int	accessTime;	int	recoveryTime;	int	cycleTime;};struct mdma_timings_t mdma_timings_33[] __pmacdata ={    { 240, 240, 480 },    { 180, 180, 360 },    { 135, 135, 270 },    { 120, 120, 240 },    { 105, 105, 210 },    {  90,  90, 180 },    {  75,  75, 150 },    {  75,  45, 120 },    {   0,   0,   0 }};struct mdma_timings_t mdma_timings_33k[] __pmacdata ={    { 240, 240, 480 },    { 180, 180, 360 },    { 150, 150, 300 },    { 120, 120, 240 },    {  90, 120, 210 },    {  90,  90, 180 },    {  90,  60, 150 },    {  90,  30, 120 },    {   0,   0,   0 }};struct mdma_timings_t mdma_timings_66[] __pmacdata ={    { 240, 240, 480 },    { 180, 180, 360 },    { 135, 135, 270 },    { 120, 120, 240 },    { 105, 105, 210 },    {  90,  90, 180 },    {  90,  75, 165 },    {  75,  45, 120 },    {   0,   0,   0 }};/* KeyLargo ATA-4 Ultra DMA timings (rounded) */struct {	int	addrSetup; /* ??? */	int	rdy2pause;	int	wrDataSetup;} kl66_udma_timings[] __pmacdata ={    {   0, 180,  120 },	/* Mode 0 */    {   0, 150,  90 },	/*      1 */    {   0, 120,  60 },	/*      2 */    {   0, 90,   45 },	/*      3 */    {   0, 90,   30 }	/*      4 */};/* UniNorth 2 ATA/100 timings */struct kauai_timing {	int	cycle_time;	u32	timing_reg;};static struct kauai_timing	kauai_pio_timings[] __pmacdata ={	{ 930	, 0x08000fff },	{ 600	, 0x08000a92 },	{ 383	, 0x0800060f },	{ 360	, 0x08000492 },	{ 330	, 0x0800048f },	{ 300	, 0x080003cf },	{ 270	, 0x080003cc },	{ 240	, 0x0800038b },	{ 239	, 0x0800030c },	{ 180	, 0x05000249 },	{ 120	, 0x04000148 }};static struct kauai_timing	kauai_mdma_timings[] __pmacdata ={	{ 1260	, 0x00fff000 },	{ 480	, 0x00618000 },	{ 360	, 0x00492000 },	{ 270	, 0x0038e000 },	{ 240	, 0x0030c000 },	{ 210	, 0x002cb000 },	{ 180	, 0x00249000 },	{ 150	, 0x00209000 },	{ 120	, 0x00148000 },	{ 0	, 0 },};static struct kauai_timing	kauai_udma_timings[] __pmacdata ={	{ 120	, 0x000070c0 },	{ 90	, 0x00005d80 },	{ 60	, 0x00004a60 },	{ 45	, 0x00003a50 },	{ 30	, 0x00002a30 },	{ 20	, 0x00002921 },	{ 0	, 0 },};static inline u32kauai_lookup_timing(struct kauai_timing* table, int cycle_time){	int i;		for (i=0; table[i].cycle_time; i++)		if (cycle_time > table[i+1].cycle_time)			return table[i].timing_reg;	return 0;}/* allow up to 256 DBDMA commands per xfer */#define MAX_DCMDS		256/*  * Wait 1s for disk to answer on IDE bus after a hard reset * of the device (via GPIO/FCR). *  * Some devices seem to "pollute" the bus even after dropping * the BSY bit (typically some combo drives slave on the UDMA * bus) after a hard reset. Since we hard reset all drives on * KeyLargo ATA66, we have to keep that delay around. I may end * up not hard resetting anymore on these and keep the delay only * for older interfaces instead (we have to reset when coming * from MacOS...) --BenH.  */#define IDE_WAKEUP_DELAY	(1*HZ)static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);static void pmac_ide_selectproc(ide_drive_t *drive);static void pmac_ide_kauai_selectproc(ide_drive_t *drive);static int pmac_ide_dma_begin (ide_drive_t *drive);#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC *//* * Below is the code for blinking the laptop LED along with hard * disk activity. */#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK/* Set to 50ms minimum led-on time (also used to limit frequency * of requests sent to the PMU */#define PMU_HD_BLINK_TIME	(HZ/50)static struct adb_request pmu_blink_on, pmu_blink_off;static spinlock_t pmu_blink_lock;static unsigned long pmu_blink_stoptime;static int pmu_blink_ledstate;static struct timer_list pmu_blink_timer;static int pmu_ide_blink_enabled;static voidpmu_hd_blink_timeout(unsigned long data){	unsigned long flags;		spin_lock_irqsave(&pmu_blink_lock, flags);	/* We may have been triggered again in a racy way, check	 * that we really want to switch it off	 */	if (time_after(pmu_blink_stoptime, jiffies))		goto done;	/* Previous req. not complete, try 100ms more */	if (pmu_blink_off.complete == 0)		mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);	else if (pmu_blink_ledstate) {		pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);		pmu_blink_ledstate = 0;	}done:	spin_unlock_irqrestore(&pmu_blink_lock, flags);}static voidpmu_hd_kick_blink(void *data, int rw){	unsigned long flags;		pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;	wmb();	mod_timer(&pmu_blink_timer, pmu_blink_stoptime);	/* Fast path when LED is already ON */	if (pmu_blink_ledstate == 1)		return;	spin_lock_irqsave(&pmu_blink_lock, flags);	if (pmu_blink_on.complete && !pmu_blink_ledstate) {		pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);		pmu_blink_ledstate = 1;	}	spin_unlock_irqrestore(&pmu_blink_lock, flags);}static intpmu_hd_blink_init(void){	struct device_node *dt;	const char *model;	/* Currently, I only enable this feature on KeyLargo based laptops,	 * older laptops may support it (at least heathrow/paddington) but	 * I don't feel like loading those venerable old machines with so	 * much additional interrupt & PMU activity...	 */	if (pmu_get_model() != PMU_KEYLARGO_BASED)		return 0;		dt = find_devices("device-tree");	if (dt == NULL)		return 0;	model = (const char *)get_property(dt, "model", NULL);	if (model == NULL)		return 0;	if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&	    strncmp(model, "iBook", strlen("iBook")) != 0)	    	return 0;		pmu_blink_on.complete = 1;	pmu_blink_off.complete = 1;	spin_lock_init(&pmu_blink_lock);	init_timer(&pmu_blink_timer);	pmu_blink_timer.function = pmu_hd_blink_timeout;	return 1;}#endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK *//* * N.B. this can't be an initfunc, because the media-bay task can * call ide_[un]register at any time. */void __pmacpmac_ide_init_hwif_ports(hw_regs_t *hw,			      unsigned long data_port, unsigned long ctrl_port,			      int *irq){	int i, ix;	if (data_port == 0)		return;	for (ix = 0; ix < MAX_HWIFS; ++ix)		if (data_port == pmac_ide[ix].regbase)			break;	if (ix >= MAX_HWIFS) {		/* Probably a PCI interface... */		for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)			hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;		hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;		return;	}	for (i = 0; i < 8; ++i)		hw->io_ports[i] = data_port + i * 0x10;	hw->io_ports[8] = data_port + 0x160;	if (irq != NULL)		*irq = pmac_ide[ix].irq;}/* * Apply the timings of the proper unit (master/slave) to the shared * timing register when selecting that unit. This version is for * ASICs with a single timing register */static void __pmacpmac_ide_selectproc(ide_drive_t *drive){	pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;	if (pmif == NULL)		return;	if (drive->select.b.unit & 0x01)		writel(pmif->timings[1],			(unsigned *)(IDE_DATA_REG+IDE_TIMING_CONFIG));	else		writel(pmif->timings[0],			(unsigned *)(IDE_DATA_REG+IDE_TIMING_CONFIG));	(void)readl((unsigned *)(IDE_DATA_REG+IDE_TIMING_CONFIG));}/* * Apply the timings of the proper unit (master/slave) to the shared * timing register when selecting that unit. This version is for * ASICs with a dual timing register (Kauai) */static void __pmacpmac_ide_kauai_selectproc(ide_drive_t *drive){	pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;	if (pmif == NULL)		return;	if (drive->select.b.unit & 0x01) {		writel(pmif->timings[1],		       (unsigned *)(IDE_DATA_REG + IDE_KAUAI_PIO_CONFIG));		writel(pmif->timings[3],		       (unsigned *)(IDE_DATA_REG + IDE_KAUAI_ULTRA_CONFIG));	} else {		writel(pmif->timings[0],		       (unsigned *)(IDE_DATA_REG + IDE_KAUAI_PIO_CONFIG));		writel(pmif->timings[2],		       (unsigned *)(IDE_DATA_REG + IDE_KAUAI_ULTRA_CONFIG));	}	(void)readl((unsigned *)(IDE_DATA_REG + IDE_KAUAI_PIO_CONFIG));}/* * Force an update of controller timing values for a given drive