?? pc300_drv.c
字號:
}void falc_init_t1(pc300_t * card, int ch){ pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; falc_t *pfalc = (falc_t *) & chan->falc; uclong falcbase = card->hw.falcbase; ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); /* Switch to T1 mode (PCM 24) */ cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD); /* Wait 20 us for setup */ udelay(20); /* Transmit Buffer Size (1 frame) */ cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0); /* Clock mode */ if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS); } else { /* Slave mode */ cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS); cpc_writeb(falcbase + F_REG(LOOP, ch), cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM); } cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI); cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) & ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1)); switch (conf->lcode) { case PC300_LC_AMI: cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_XC1 | FMR0_RC1); /* Clear Channel register to ON for all channels */ cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff); cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff); cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff); break; case PC300_LC_B8ZS: cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1); break; case PC300_LC_NRZ: cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00); break; } cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS); cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0)); /* Set interface mode to 2 MBPS */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD); switch (conf->fr_mode) { case PC300_FR_ESF: pfalc->multiframe_mode = 0; cpc_writeb(falcbase + F_REG(FMR4, ch), cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1); cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CRC | FMR1_EDL); cpc_writeb(falcbase + F_REG(XDL1, ch), 0); cpc_writeb(falcbase + F_REG(XDL2, ch), 0); cpc_writeb(falcbase + F_REG(XDL3, ch), 0); cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP); break; case PC300_FR_D4: pfalc->multiframe_mode = 1; cpc_writeb(falcbase + F_REG(FMR4, ch), cpc_readb(falcbase + F_REG(FMR4, ch)) & ~(FMR4_FM1 | FMR4_FM0)); cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP); break; } /* Enable Automatic Resynchronization */ cpc_writeb(falcbase + F_REG(FMR4, ch), cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO); /* Transmit Automatic Remote Alarm */ cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA); /* Channel translation mode 1 : one to one */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM); /* No signaling */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM); cpc_writeb(falcbase + F_REG(FMR5, ch), cpc_readb(falcbase + F_REG(FMR5, ch)) & ~(FMR5_EIBR | FMR5_SRS)); cpc_writeb(falcbase + F_REG(CCR1, ch), 0); cpc_writeb(falcbase + F_REG(LIM1, ch), cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1); switch (conf->lbo) { /* Provides proper Line Build Out */ case PC300_LBO_0_DB: cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja)); cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a); cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f); cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); break; case PC300_LBO_7_5_DB: cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja)); cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11); cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02); cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); break; case PC300_LBO_15_DB: cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja)); cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e); cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01); cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); break; case PC300_LBO_22_5_DB: cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja)); cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09); cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01); cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20); break; } /* Transmit Clock-Slot Offset */ cpc_writeb(falcbase + F_REG(XC0, ch), cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01); /* Transmit Time-slot Offset */ cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e); /* Receive Clock-Slot offset */ cpc_writeb(falcbase + F_REG(RC0, ch), 0x05); /* Receive Time-slot offset */ cpc_writeb(falcbase + F_REG(RC1, ch), 0x00); /* LOS Detection after 176 consecutive 0s */ cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a); /* LOS Recovery after 22 ones in the time window of PCD */ cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15); cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f); if (conf->fr_mode == PC300_FR_ESF_JAPAN) { cpc_writeb(falcbase + F_REG(RC1, ch), cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80); } falc_close_all_timeslots(card, ch);}void falc_init_e1(pc300_t * card, int ch){ pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; falc_t *pfalc = (falc_t *) & chan->falc; uclong falcbase = card->hw.falcbase; ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0); /* Switch to E1 mode (PCM 30) */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD); /* Clock mode */ if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */ cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS); } else { /* Slave mode */ cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS); } cpc_writeb(falcbase + F_REG(LOOP, ch), cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM); cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI); cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) & ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1)); switch (conf->lcode) { case PC300_LC_AMI: cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_XC1 | FMR0_RC1); break; case PC300_LC_HDB3: cpc_writeb(falcbase + F_REG(FMR0, ch), cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1); break; case PC300_LC_NRZ: break; } cpc_writeb(falcbase + F_REG(LIM0, ch), cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0)); /* Set interface mode to 2 MBPS */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD); cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18); cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03); cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00); switch (conf->fr_mode) { case PC300_FR_MF_CRC4: pfalc->multiframe_mode = 1; cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0); cpc_writeb(falcbase + F_REG(FMR3, ch), cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW); /* MultiFrame Resynchronization */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS); /* Automatic Loss of Multiframe > 914 CRC errors */ cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF); /* S1 and SI1/SI2 spare Bits set to 1 */ cpc_writeb(falcbase + F_REG(XSP, ch), cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS); cpc_writeb(falcbase + F_REG(XSP, ch), cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP); cpc_writeb(falcbase + F_REG(XSP, ch), cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15); /* Automatic Force Resynchronization */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR); /* Transmit Automatic Remote Alarm */ cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA); /* Transmit Spare Bits for National Use (Y, Sn, Sa) */ cpc_writeb(falcbase + F_REG(XSW, ch), cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4); break; case PC300_FR_MF_NON_CRC4: case PC300_FR_D4: pfalc->multiframe_mode = 0; cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) & ~(FMR2_RFS1 | FMR2_RFS0)); cpc_writeb(falcbase + F_REG(XSW, ch), cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS); cpc_writeb(falcbase + F_REG(XSP, ch), cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF); /* Automatic Force Resynchronization */ cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR); /* Transmit Automatic Remote Alarm */ cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA); /* Transmit Spare Bits for National Use (Y, Sn, Sa) */ cpc_writeb(falcbase + F_REG(XSW, ch), cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4); break; case PC300_FR_UNFRAMED: pfalc->multiframe_mode = 0; cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) & ~(FMR2_RFS1 | FMR2_RFS0)); cpc_writeb(falcbase + F_REG(XSP, ch), cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0); cpc_writeb(falcbase + F_REG(XSW, ch), cpc_readb(falcbase + F_REG(XSW, ch)) & ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4)); cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) | (FMR2_RTM | FMR2_DAIS)); cpc_writeb(falcbase + F_REG(FMR2, ch), cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA); cpc_writeb(falcbase + F_REG(FMR1, ch), cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR); pfalc->sync = 1; cpc_writeb(falcbase + card->hw.cpld_reg2, cpc_readb(falcbase + card->hw.cpld_reg2) | (CPLD_REG2_FALC_LED2 << (2 * ch))); break; } /* No signaling */ cpc_writeb(falcbase + F_REG(XSP, ch), cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN); cpc_writeb(falcbase + F_REG(CCR1, ch), 0); cpc_writeb(falcbase + F_REG(LIM1, ch), cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1); cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja)); /* Transmit Clock-Slot Offset */ cpc_writeb(falcbase + F_REG(XC0, ch), cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01); /* Transmit Time-slot Offset */ cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e); /* Receive Clock-Slot offset */ cpc_writeb(falcbase + F_REG(RC0, ch), 0x05); /* Receive Time-slot offset */ cpc_writeb(falcbase + F_REG(RC1, ch), 0x00); /* LOS Detection after 176 consecutive 0s */ cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a); /* LOS Recovery after 22 ones in the time window of PCD */ cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15); cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f); falc_close_all_timeslots(card, ch);}void falc_init_hdlc(pc300_t * card, int ch){ uclong falcbase = card->hw.falcbase; pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; /* Enable transparent data transfer */ if (conf->fr_mode == PC300_FR_UNFRAMED) { cpc_writeb(falcbase + F_REG(MODE, ch), 0); } else { cpc_writeb(falcbase + F_REG(MODE, ch), cpc_readb(falcbase + F_REG(MODE, ch)) | (MODE_HRAC | MODE_MDS2)); cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff); cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff); cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff); cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff); } /* Tx/Rx reset */ falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES); /* Enable interrupt sources */ falc_intr_enable(card, ch);}void te_config(pc300_t * card, int ch){ pc300ch_t *chan = (pc300ch_t *) & card->chan[ch]; pc300chconf_t *conf = (pc300chconf_t *) & chan->conf; falc_t *pfalc = (falc_t *) & chan->falc; uclong falcbase = card->hw.falcbase; ucchar dummy; unsigned long flags; memset(pfalc, 0, sizeof(falc_t)); switch (conf->media) { case IF_IFACE_T1: pfalc->num_channels = NUM_OF_T1_CHANNELS; pfalc->offset = 1; break; case IF_IFACE_E1: pfalc->num_channels = NUM_OF_E1_CHANNELS; pfalc->offset = 0; break; } if (conf->tslot_bitmap == 0xffffffffUL) pfalc->full_bandwidth = 1; else pfalc->full_bandwidth = 0; CPC_LOCK(card, flags);?? 快捷鍵說明
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