/* Reset the FALC chip */	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |		   (CPLD_REG1_FALC_RESET << (2 * ch)));	udelay(10000);	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &		   ~(CPLD_REG1_FALC_RESET << (2 * ch)));	if (conf->media == IF_IFACE_T1) {		falc_init_t1(card, ch);	} else {		falc_init_e1(card, ch);	}	falc_init_hdlc(card, ch);	if (conf->rx_sens == PC300_RX_SENS_SH) {		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);	} else {		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);	}	cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,		   cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |		   ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));	/* Clear all interrupt registers */	dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +		cpc_readb(falcbase + F_REG(FISR1, ch)) +		cpc_readb(falcbase + F_REG(FISR2, ch)) +		cpc_readb(falcbase + F_REG(FISR3, ch));	CPC_UNLOCK(card, flags);}void falc_check_status(pc300_t * card, int ch, unsigned char frs0){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	uclong falcbase = card->hw.falcbase;	/* Verify LOS */	if (frs0 & FRS0_LOS) {		if (!pfalc->red_alarm) {			pfalc->red_alarm = 1;			pfalc->los++;			if (!pfalc->blue_alarm) {				// EVENT_FALC_ABNORMAL				if (conf->media == IF_IFACE_T1) {					/* Disable this interrupt as it may otherwise interfere 					 * with other working boards. */					cpc_writeb(falcbase + F_REG(IMR0, ch), 						   cpc_readb(falcbase + F_REG(IMR0, ch))						   | IMR0_PDEN);				}				falc_disable_comm(card, ch);				// EVENT_FALC_ABNORMAL			}		}	} else {		if (pfalc->red_alarm) {			pfalc->red_alarm = 0;			pfalc->losr++;		}	}	if (conf->fr_mode != PC300_FR_UNFRAMED) {		/* Verify AIS alarm */		if (frs0 & FRS0_AIS) {			if (!pfalc->blue_alarm) {				pfalc->blue_alarm = 1;				pfalc->ais++;				// EVENT_AIS				if (conf->media == IF_IFACE_T1) {					/* Disable this interrupt as it may otherwise interfere with                       other working boards. */					cpc_writeb(falcbase + F_REG(IMR0, ch),						   cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);				}				falc_disable_comm(card, ch);				// EVENT_AIS			}		} else {			pfalc->blue_alarm = 0;		}		/* Verify LFA */		if (frs0 & FRS0_LFA) {			if (!pfalc->loss_fa) {				pfalc->loss_fa = 1;				pfalc->lfa++;				if (!pfalc->blue_alarm && !pfalc->red_alarm) {					// EVENT_FALC_ABNORMAL					if (conf->media == IF_IFACE_T1) {						/* Disable this interrupt as it may otherwise 						 * interfere with other working boards. */						cpc_writeb(falcbase + F_REG(IMR0, ch),							   cpc_readb(falcbase + F_REG(IMR0, ch))							   | IMR0_PDEN);					}					falc_disable_comm(card, ch);					// EVENT_FALC_ABNORMAL				}			}		} else {			if (pfalc->loss_fa) {				pfalc->loss_fa = 0;				pfalc->farec++;			}		}		/* Verify LMFA */		if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {			/* D4 or CRC4 frame mode */			if (!pfalc->loss_mfa) {				pfalc->loss_mfa = 1;				pfalc->lmfa++;				if (!pfalc->blue_alarm && !pfalc->red_alarm &&				    !pfalc->loss_fa) {					// EVENT_FALC_ABNORMAL					if (conf->media == IF_IFACE_T1) {						/* Disable this interrupt as it may otherwise 						 * interfere with other working boards. */						cpc_writeb(falcbase + F_REG(IMR0, ch),							   cpc_readb(falcbase + F_REG(IMR0, ch))							   | IMR0_PDEN);					}					falc_disable_comm(card, ch);					// EVENT_FALC_ABNORMAL				}			}		} else {			pfalc->loss_mfa = 0;		}		/* Verify Remote Alarm */		if (frs0 & FRS0_RRA) {			if (!pfalc->yellow_alarm) {				pfalc->yellow_alarm = 1;				pfalc->rai++;				if (pfalc->sync) {					// EVENT_RAI					falc_disable_comm(card, ch);					// EVENT_RAI				}			}		} else {			pfalc->yellow_alarm = 0;		}	} /* if !PC300_UNFRAMED */	if (pfalc->red_alarm || pfalc->loss_fa ||	    pfalc->loss_mfa || pfalc->blue_alarm) {		if (pfalc->sync) {			pfalc->sync = 0;			chan->d.line_off++;			cpc_writeb(falcbase + card->hw.cpld_reg2,				   cpc_readb(falcbase + card->hw.cpld_reg2) &				   ~(CPLD_REG2_FALC_LED2 << (2 * ch)));		}	} else {		if (!pfalc->sync) {			pfalc->sync = 1;			chan->d.line_on++;			cpc_writeb(falcbase + card->hw.cpld_reg2,				   cpc_readb(falcbase + card->hw.cpld_reg2) |				   (CPLD_REG2_FALC_LED2 << (2 * ch)));		}	}	if (pfalc->sync && !pfalc->yellow_alarm) {		if (!pfalc->active) {			// EVENT_FALC_NORMAL			if (pfalc->loop_active) {				return;			}			if (conf->media == IF_IFACE_T1) {				cpc_writeb(falcbase + F_REG(IMR0, ch),					   cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);			}			falc_enable_comm(card, ch);			// EVENT_FALC_NORMAL			pfalc->active = 1;		}	} else {		if (pfalc->active) {			pfalc->active = 0;		}	}}void falc_update_stats(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	uclong falcbase = card->hw.falcbase;	ucshort counter;	counter = cpc_readb(falcbase + F_REG(FECL, ch));	counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;	pfalc->fec += counter;	counter = cpc_readb(falcbase + F_REG(CVCL, ch));	counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;	pfalc->cvc += counter;	counter = cpc_readb(falcbase + F_REG(CECL, ch));	counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;	pfalc->cec += counter;	counter = cpc_readb(falcbase + F_REG(EBCL, ch));	counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;	pfalc->ebc += counter;	if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {		mdelay(10);		counter = cpc_readb(falcbase + F_REG(BECL, ch));		counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;		pfalc->bec += counter;		if (((conf->media == IF_IFACE_T1) &&		     (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&		     (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))		    ||		    ((conf->media == IF_IFACE_E1) &&		     (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {			pfalc->prbs = 2;		} else {			pfalc->prbs = 1;		}	}}/*---------------------------------------------------------------------------- * falc_remote_loop *---------------------------------------------------------------------------- * Description:	In the remote loopback mode the clock and data recovered *		from the line inputs RL1/2 or RDIP/RDIN are routed back *		to the line outputs XL1/2 or XDOP/XDON via the analog *		transmitter. As in normal mode they are processsed by *		the synchronizer and then sent to the system interface. *---------------------------------------------------------------------------- */void falc_remote_loop(pc300_t * card, int ch, int loop_on){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	uclong falcbase = card->hw.falcbase;	if (loop_on) {		// EVENT_FALC_ABNORMAL		if (conf->media == IF_IFACE_T1) {			/* Disable this interrupt as it may otherwise interfere with 			 * other working boards. */			cpc_writeb(falcbase + F_REG(IMR0, ch),				   cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);		}		falc_disable_comm(card, ch);		// EVENT_FALC_ABNORMAL		cpc_writeb(falcbase + F_REG(LIM1, ch),			   cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);		pfalc->loop_active = 1;	} else {		cpc_writeb(falcbase + F_REG(LIM1, ch),			   cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);		pfalc->sync = 0;		cpc_writeb(falcbase + card->hw.cpld_reg2,			   cpc_readb(falcbase + card->hw.cpld_reg2) &			   ~(CPLD_REG2_FALC_LED2 << (2 * ch)));		pfalc->active = 0;		falc_issue_cmd(card, ch, CMDR_XRES);		pfalc->loop_active = 0;	}}/*---------------------------------------------------------------------------- * falc_local_loop *---------------------------------------------------------------------------- * Description: The local loopback mode disconnects the receive lines  *		RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the *		signals coming from the line the data provided by system *		interface are routed through the analog receiver back to *		the system interface. The unipolar bit stream will be *		undisturbed transmitted on the line. Receiver and transmitter *		coding must be identical. *---------------------------------------------------------------------------- */void falc_local_loop(pc300_t * card, int ch, int loop_on){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	falc_t *pfalc = (falc_t *) & chan->falc;	uclong falcbase = card->hw.falcbase;	if (loop_on) {		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);		pfalc->loop_active = 1;	} else {		cpc_writeb(falcbase + F_REG(LIM0, ch),			   cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);		pfalc->loop_active = 0;	}}/*---------------------------------------------------------------------------- * falc_payload_loop *---------------------------------------------------------------------------- * Description: This routine allows to enable/disable payload loopback. *		When the payload loop is activated, the received 192 bits *		of payload data will be looped back to the transmit *		direction. The framing bits, CRC6 and DL bits are not  *		looped. They are originated by the FALC-LH transmitter. *---------------------------------------------------------------------------- */void falc_payload_loop(pc300_t * card, int ch, int loop_on){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	falc_t *pfalc = (falc_t *) & chan->falc;	uclong falcbase = card->hw.falcbase;	if (loop_on) {		// EVENT_FALC_ABNORMAL		if (conf->media == IF_IFACE_T1) {			/* Disable this interrupt as it may otherwise interfere with 			 * other working boards. */			cpc_writeb(falcbase + F_REG(IMR0, ch),				   cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);		}		falc_disable_comm(card, ch);		// EVENT_FALC_ABNORMAL		cpc_writeb(falcbase + F_REG(FMR2, ch),			   cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);		if (conf->media == IF_IFACE_T1) {			cpc_writeb(falcbase + F_REG(FMR4, ch),				   cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);		} else {			cpc_writeb(falcbase + F_REG(FMR5, ch),				   cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);		}		falc_open_all_timeslots(card, ch);		pfalc->loop_active = 2;	} else {		cpc_writeb(falcbase + F_REG(FMR2, ch),			   cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);		if (conf->media == IF_IFACE_T1) {			cpc_writeb(falcbase + F_REG(FMR4, ch),				   cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);		} else {			cpc_writeb(falcbase + F_REG(FMR5, ch),				   cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);		}		pfalc->sync = 0;		cpc_writeb(falcbase + card->hw.cpld_reg2,			   cpc_readb(falcbase + card->hw.cpld_reg2) &			   ~(CPLD_REG2_FALC_LED2 << (2 * ch)));		pfalc->active = 0;		falc_issue_cmd(card, ch, CMDR_XRES);		pfalc->loop_active = 0;	}}/*---------------------------------------------------------------------------- * turn_off_xlu *---------------------------------------------------------------------------- * Description:	Turns XLU bit off in the proper register *---------------------------------------------------------------------------- */void turn_off_xlu(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	uclong falcbase = card->hw.falcbase;	if (conf->media == IF_IFACE_T1) {		cpc_writeb(falcbase + F_REG(FMR5, ch),			   cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);	} else {		cpc_writeb(falcbase + F_REG(FMR3, ch),			   cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);	}}/*---------------------------------------------------------------------------- * turn_off_xld *---------------------------------------------------------------------------- * Description: Turns XLD bit off in the proper register *---------------------------------------------------------------------------- */void turn_off_xld(pc300_t * card, int ch){	pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];	pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;	uclong falcbase = card->hw.falcbase;	if (conf->media == IF_IFACE_T1) {		cpc_writeb(falcbase + F_REG(FMR5, ch),			   cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);	} else {		cpc_writeb(falcbase + F_REG(FMR3, ch),			   cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);	}